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Standby mode control
STBYEXIT
Audio output
HPOP
HPON
SPHMT
General-purpose GPO pins
GP00
GP01
GP02
GP03
GP04
GP05
GP06
External SPI flash memory interface
SMCS
SMSCK
SMSI
SMSO
System clock
CLKI
OSCI
OSCO
CLKSEL
OSCEN
Hardware reset
NRESET
Mode setting
SNGLEND
HMTPOL
S1V3G340 Hardware Specification
(Rev. 1.0)
Downloaded from
Elcodis.com
electronic components distributor
41
I
IC
Z
24
O
T2
Z
16
O
T2
Z
See
5
O
O1
Function
12
O
O1
L
17
O
O1
L
18
O
O1
L
19
O
O1
L
20
O
O1
L
21
O
O1
L
22
O
O1
L
33
O
O1
L
50
O
O2
L
38
I
IC
Z
37
O
O1
L
31
I
IC
Z
36
I
LLIN
Z
35
O
LLOT
-
25
I
IC
Z
27
I
IC
Z
8
I
IH
Z
29
I
IC
Z
28
I
IC
Z
STANDBY mode exit control Input
HVDD
(L: Exit STANDBY mode,
H: Continue STANDBY mode)
HVDD
Audio output
Audio output
HVDD
(Can be set so that output stops when
SNGLEND = H (L level).)
PWM output interval output
(Active only while PWM waveform is output
from output pin HPO.
Inactive for NRESET = L.
HVDD
Active level polarity can be defined to suit input
pin HMTPOL settings.
L active for HMTPOL = L,
H active for HMTPOL = H)
HVDD
General-purpose output
HVDD
General-purpose output
HVDD
General-purpose output
HVDD
General-purpose output
HVDD
General-purpose output
HVDD
General-purpose output
HVDD
General-purpose output
HVDD
SPI flash memory chip select
HVDD
SPI flash memory serial clock
HVDD
SPI flash memory serial data in
HVDD
SPI flash memory serial data out
HVDD
Clock input (See section 5.2)
-
Oscillator connector pin (See section 5.2)
-
Oscillator connector pin (See section 5.2)
System clock frequency selection
HVDD
(L: 32.768 kHz, H: 12.288 MHz)
(See section 5.2)
System clock source selection
HVDD
(L: CLKI input, H: oscillator (OSCI/OSCO))
(See section 5.2)
HVDD
Hardware reset input (L active)
Audio output mode selection
HVDD
(L: differential output, H: single end output)
SPHMT polarity selection
HVDD
(L active for L: SPHMT, H active for H: SPHMT)
EPSON
4. Pin Description
5
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