Table of Contents
Advertisement
Schematic Diagrams
PS8625
D04_Reflash_0910_Alex
D04_Reflash_0910_Alex
5
iGP_eDP_AUX#
5
iGP_eDP_AUX
Sheet 15 of 66
PS8625
5
iGP_eDP_TX0
5
iGP_eDP_TX#0
5
iGP_eDP_TX1
5
iGP_eDP_TX#1
1
CPU EDP BRIGHTNESS
Power On Configuration
D01a_1009_Alex
GND
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K
L: 8-bit LVDS, VESA mapping
M: 8-bit LVDS, JEIDA mapping
H: 6-bit LVDS, both VESA and JEIDA mapping
RLV_LNK/GPIO0
RLV_LNK: LVDS single link or dual link selection, internal pull-down ~80K
L: Single link LVDS
H: Dual link LVDS
ENPVCC
I2C_ADDR: I2C Slave address selection, internal pull-down ~80K
L: 0x10h~0x1Fh
H: 0x90h~0x9Fh
B - 16 PS8625
D04_Reflash_0910_Alex
L56
L56
L55
L55
HCB1005KF-121T20
HCB1005KF-121T20
HCB1005KF-121T20
HCB1005KF-121T20
3.3VS
VDDIO
3.3VS
C170
C170
C533
C533
C169
C169
C438
C438
3.3VS
*100K_04
*100K_04
R117
R117
d
R209
R209
*0_04
*0_04
D04_Reflash_0910_Alex
C102 0.1u_10V_X7R_04
C102 0.1u_10V_X7R_04
DAUXn
R210
R210
*0_04
*0_04
C103 0.1u_10V_X7R_04
C103 0.1u_10V_X7R_04
DAUXp
*100K_04
*100K_04
R118
R118
R225
R225
*0_04
*0_04
R256
R256
*0_04
*0_04
D04_Reflash_0910_Alex
R202
R202
*0_04
*0_04
R220
R220
*0_04
*0_04
C51
C51
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX0p
R203
R203
*0_04
*0_04
R211
R211
*0_04
*0_04
C60
C60
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX0n
R204
R204
*0_04
*0_04
R212
R212
*0_04
*0_04
C63
C63
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX1p
R207
R207
*0_04
*0_04
R219
R219
*0_04
*0_04
C66
C66
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX1n
R174
R174
*0_04
*0_04
Closed to J_LCD2
5
EDP_DISP_UTIL
R179
R179
0_04
0_04
D01A_1016_Alex
22
L_BRIGHTNESS_R
R172
R172
*0_04
*0_04
R1140
R1140
*0_04
*0_04
PW MI
PW MO
34
BRIGHTNESS
EC BRIGHTNESS
R121
R121
100K_04
100K_04
D04_Reflash_0910_Alex
TDB_Alex
R97
R97
0_04
0_04
PS_HPD
14
HPD_L
R115
R115
*100K_04
*100K_04
R175
R175
*4.7K_04
*4.7K_04
R176
R176
4.7K_04
4.7K_04
RLV_CFG
VDDIO
R177
R177
4.7K_04
4.7K_04
VDDIO
R178
R178
*4.7K_04
*4.7K_04
VDDIO
1
BCIHP0420TB-2R2M
BCIHP0420TB-2R2M
L68
L68
HCB1005KF-121T20
HCB1005KF-121T20
VDDIOX
SW _OUT
L74
L74
VDD12
VDDRX
C534
C534
C195
C195
PGND
Switching Regulator Layout Guideline
W
>
^t Khd W
W
W
d
^t Khd
d
'Ey
W
W
W
'E
W^
'E
'E
'E
'E
W
W
&
s/Ky
s/Ky
d
'E
&
s/Ky
'E
&
/
VDDIO
W
>
s/Ky
W^
D01a_1009_Alex
LVDS_iGP_AUX#_C 14
LVDS_iGP_AUX_C 14
LVDS_iGP_TX0_C 14
LVDS_iGP_TX#0_C 14
U65
U65
DAUXn
1
LVDS_iGP_TX1_C 14
DAUXn
TA1n
DAUXp
2
DAUXp
TA1p
GNDA
3
LVDS_iGP_TX#1_C 14
GND
TB1n
DRX0p
4
DRX0p
TB1p
DRX0n
5
DRX0n
VDDIO
VDDRX
6
RTL8411-CG
RTL8411-CG
VDDRX
TC1n
DRX1p
7
DRX1p
TC1p
8
DRX1n
DRX1n
TCK1n
RST#
9
RST#
TCK1p
C198
C198
C197
C197
PD#
10
PD#
ENPVCC/I2C_ADDR
PS_HPD
11
HPD
TD1n
12
PW MO
PWMO
TD1p
VDDIOX
13
VDDIOX
DDC_SDA
VDDIOX
14
VDDIOX
DDC_SCL
GNDA
57
Epad
Noe:
R13: LVDS output swing control
C231
C231
C233
C233
4.99K for default swing, change the value for swing adjust
13,32,34,35
13,32,34,35
3.3VS
3,5,9,10,11,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30,32,33,34,35,36,37,41,44,46,61
3.3V
2,14,19,29,30,32,36,37,39,41,42
1
ENPVCC
PS_PANEL_EN 14
ENBLT
PS_BKL_EN 14
PW MO
PW MO
14
LVDS_U0N
LVDS_U0N 14
LVDS_U0P
LVDS_U0P 14
C267
C267
LVDS_U1N
LVDS_U1N 14
LVDS_U1P
LVDS_U1P 14
LVDS_U2N
LVDS_U2N 14
LVDS_U2P
LVDS_U2P 14
LVDS_UCLKN
LVDS_UCLKN 14
LVDS_UCLKP
LVDS_UCLKP 14
'E
'E
TD0n
TD0p
LVDS_L0N
LVDS_L0N 14
LVDS_L0P
LVDS_L0P 14
LVDS_L1N
LVDS_L1N 14
LVDS_L1P
LVDS_L1P 14
Note:
LVDS_L2N
LVDS_L2N 14
The decoupling caps C9, C15, C16, C17, C18, C21
LVDS_L2P
LVDS_L2P 14
shall be close to the power pins as possible
LVDS_LCLKN
LVDS_LCLKN 14
LVDS_LCLKP
LVDS_LCLKP 14
TD1n
TD1p
VDDIO
D01a_1009_Alex
42
LVDS_U0N
41
LVDS_U0P
40
LVDS_U1N
39
LVDS_U1P
R805
R805
38
VDDIO
GND
37
LVDS_U2N
C270
C270
*15mil_short_06
*15mil_short_06
W
36
LVDS_U2P
35
LVDS_UCLKN
34
LVDS_UCLKP
33
ENPVCC
32
TD1n
31
TD1p
30
DDC_SDA
LVDS_DDC_DAT 14
29
DDC_SCL
LVDS_DDC_CLK 14
VDDIO
D01A_1016_Alex
/
WZKD
VDDIO
8
R150
R150
0_04
0_04
RLV_LNK/GPIO0
7
6
CSCL/MSCL
SMC_VGA_THERM
CSDA/MSDA
5
SMD_VGA_THERM
R165
R165
0_04
0_04
I2C_CFG = "H"
EEPROM for Initial Code
I2C Address: 0xA0
Suggest minimum 2Kbit
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[15 ]PARADE PS8625
[15 ]PARADE PS8625
[15 ]PARADE PS8625
Size
Size
Size
Document Number
Document Number
Document Number
6-71-P15S0-DA3A
6-71-P15S0-DA3A
6-71-P15S0-DA3A
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date:
Date:
Date:
Thursday, March 06, 2014
Thursday, March 06, 2014
Thursday, March 06, 2014
Sheet
Sheet
Sheet
GNDA
1
U77
U77
1
VCC
E0
2
WC#
E1
3
SCL
E2
4
SDA
VSS
*M24C02~M24C16
*M24C02~M24C16
Rev
Rev
Rev
1.0
1.0
1.0
15
15
15
of
of
of
66
66
66
Advertisement
Table of Contents
