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Schematic Diagrams
DDR3 CHB SO-DIMM_1
Channel B SO-DIMM 1[RAM4]
D
Sheet 11 of 66
DDR3 CHB SO-
C
DIMM _1
B
A
B - 12 DDR3 CHB SO-DIMM_1
5
4
CHANGE TO STANDARD
JDIMM2A
JDIMM2A
4,12
M_B_B[15:0]
M_B_B0
98
A0
M_B_B1
97
A1
M_B_B2
96
A2
95
M_B_B3
A3
M_B_B4
92
A4
M_B_B5
91
A5
M_B_B6
90
A6
86
M_B_B7
A7
M_B_B8
89
A8
M_B_B9
85
A9
M_B_B10
107
A10/AP
84
M_B_B11
A11
M_B_B12
83
A12/BC#
M_B_B13
119
A13
M_B_B14
80
A14
78
M_B_B15
A15
109
4,12
M_B_BS0
BA0
108
4,12
M_B_BS1
BA1
79
4,12
M_B_BS2
BA2
114
4
M_B_CS#2
S0#
121
4
M_B_CS#3
S1#
101
4
M_B_CLK_DDR2
CK0
103
4
M_B_CLK_DDR#2
CK0#
102
4
M_B_CLK_DDR3
CK1
104
4
M_B_CLK_DDR#3
CK1#
73
4
M_B_CKE2
CKE0
74
4
M_B_CKE3
CKE1
115
4,12
M_B_CAS#
CAS#
110
4,12
M_B_RAS#
RAS#
113
4,12
M_B_W E#
WE#
CHB_SA0_DIM0
197
SA0
CHB_SA1_DIM0
201
SA1
202
9,10,12,20,32
SMB_CLK
SCL
200
9,10,12,20,32
SMB_DATA
SDA
116
4
M_B_ODT2
ODT0
120
4
M_B_ODT3
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
4,12
M_B_DQS[7:0]
M_B_DQS0
12
DQS0
M_B_DQS1
29
DQS1
M_B_DQS2
47
DQS2
M_B_DQS3
64
DQS3
M_B_DQS4
137
DQS4
M_B_DQS5
154
DQS5
M_B_DQS6
171
DQS6
M_B_DQS7
188
DQS7
4,12
M_B_DQS#[7:0]
M_B_DQS#0
10
DQS0#
M_B_DQS#1
27
DQS1#
M_B_DQS#2
45
DQS2#
M_B_DQS#3
62
DQS3#
M_B_DQS#4
135
DQS4#
M_B_DQS#5
152
DQS5#
M_B_DQS#6
169
DQS6#
M_B_DQS#7
186
DQS7#
DDRRK-20401-TR4B
DDRRK-20401-TR4B
VDDQ
C452
C452
C453
C453
C456
C456
C463
C463
C578
C578
C580
C580
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
1u_6.3V_X5R_04
1u_6.3V_X5R_04
10u_6.3V_X5R_06
10u_6.3V_X5R_06
1u_6.3V_X5R_04
1u_6.3V_X5R_04
VDDQ
C454
C454
C484
C484
C466
C466
C574
C574
C576
C576
C588
C588
C566
C566
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
5
4
3
M_B_DQ[63:0] 4,12
5
M_B_DQ0
DQ0
7
M_B_DQ1
DQ1
15
M_B_DQ2
DQ2
17
M_B_DQ3
DQ3
4
M_B_DQ4
DQ4
6
M_B_DQ5
DQ5
16
M_B_DQ6
DQ6
18
M_B_DQ7
DQ7
21
M_B_DQ8
DQ8
23
M_B_DQ9
DQ9
33
M_B_DQ10
DQ10
35
M_B_DQ11
DQ11
22
M_B_DQ12
DQ12
24
M_B_DQ13
DQ13
34
M_B_DQ14
DQ14
36
M_B_DQ15
DQ15
39
M_B_DQ16
DQ16
41
M_B_DQ17
DQ17
51
M_B_DQ18
3.3VS
DQ18
53
M_B_DQ19
DQ19
40
M_B_DQ20
DQ20
42
M_B_DQ21
DQ21
50
M_B_DQ22
C563
C563
DQ22
52
M_B_DQ23
DQ23
57
M_B_DQ24
1u_6.3V_X5R_04
1u_6.3V_X5R_04
DQ24
59
M_B_DQ25
DQ25
67
M_B_DQ26
DQ26
69
M_B_DQ27
DQ27
56
M_B_DQ28
DQ28
58
M_B_DQ29
DQ29
68
M_B_DQ30
DQ30
9,10,12
TS#_DIMM0_1
70
M_B_DQ31
DQ31
3,9,10,12
DDR3_DRAMRST#
129
M_B_DQ32
DQ32
131
M_B_DQ33
C228
C228
DQ33
141
M_B_DQ34
R607
R607
24.9_1%_04
24.9_1%_04
C212
C212
DQ34
143
M_B_DQ35
DQ35
4,12
MVREF_DQ_DIMMB
130
M_B_DQ36
D02
DQ36
132
M_B_DQ37
R531
R531
20mils
DQ37
4,9
SM_VREF_R
140
M_B_DQ38
DQ38
142
M_B_DQ39
DQ39
147
M_B_DQ40
C492
C492
DQ40
149
M_B_DQ41
R606
R606
24.9_1%_04
24.9_1%_04
C498
C498
DQ41
157
M_B_DQ42
DQ42
159
M_B_DQ43
DQ43
146
M_B_DQ44
DQ44
148
M_B_DQ45
DQ45
158
M_B_DQ46
DQ46
160
M_B_DQ47
DQ47
163
M_B_DQ48
DQ48
3.3VS
165
M_B_DQ49
DQ49
175
M_B_DQ50
DQ50
177
M_B_DQ51
DQ51
164
M_B_DQ52
RN8
RN8
DQ52
166
M_B_DQ53
10K_8P4R_04
10K_8P4R_04
DQ53
174
M_B_DQ54
1
8
CHB_SA0_DIM0
DQ54
176
M_B_DQ55
2
7
CHB_SA1_DIM0
DQ55
181
M_B_DQ56
3
6
CHB_SA0_DIM1
CHB_SA0_DIM1 12
DQ56
183
M_B_DQ57
4
5
CHB_SA1_DIM1
DQ57
CHB_SA1_DIM1 12
191
M_B_DQ58
DQ58
193
M_B_DQ59
DQ59
180
M_B_DQ60
DQ60
182
M_B_DQ61
DQ61
192
M_B_DQ62
DQ62
194
M_B_DQ63
CHA_DIMM0=00
DQ63
CHA_DIMM1=01
CHB_DIMM0=10
CHB_DIMM1=11
VDDQ
C582
C582
C584
C584
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
VTT_MEM
C568
C568
C572
C572
C586
C586
C508
C508
C545
C545
C518
C518
C517
C517
0.1u_10V_X5R_04
0.1u_10V_X5R_04
10u_6.3V_X5R_06
10u_6.3V_X5R_06
1u_6.3V_X5R_04
1u_6.3V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
3
2
1
JDIMM2B
JDIMM2B
VDDQ
75
44
VDD1
VSS16
76
48
VDD2
VSS17
81
49
VDD3
VSS18
82
54
VDD4
VSS19
87
55
VDD5
VSS20
88
60
VDD6
VSS21
93
61
VDD7
VSS22
94
65
VDD8
VSS23
99
66
VDD9
VSS24
100
71
VDD10
VSS25
105
72
VDD11
VSS26
106
127
VDD12
VSS27
111
128
20mils
VDD13
VSS28
112
133
VDD14
VSS29
117
134
VDD15
VSS30
118
138
VDD16
VSS31
123
139
VDD17
VSS32
C601
C601
124
144
VDD18
VSS33
145
VSS34
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
199
150
VDDSPD
VSS35
151
VSS36
77
155
NC1
VSS37
122
156
NC2
VSS38
125
161
NCTEST
VSS39
162
VSS40
198
167
EVENT#
VSS41
30
168
RESET#
VSS42
172
VSS43
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
173
20mils
VSS44
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
1
178
VREF_DQ
VSS45
126
179
VREF_CA
VSS46
MRT Test Fail
Gary
184
VSS47
*0_04
*0_04
MVREF_CA_DIMMB_R
185
VSS48
20mils
2
189
VSS1
VSS49
3
190
VSS2
VSS50
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
8
195
VSS3
VSS51
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
9
196
VSS4
VSS52
13
VSS5
14
VSS6
19
VSS7
VTT_MEM
20
VSS8
25
VSS9
26
203
VSS10
VTT1
31
204
VSS11
VTT2
32
VSS12
37
GND1
VSS13
G1
38
GND2
VSS14
G2
43
VSS15
DDRRK-20401-TR4B
DDRRK-20401-TR4B
CLOSE TO SO-DIMM
CRB 0905
R532
R532
1K_1%_04
1K_1%_04
MVREF_CA_DIMMB_R
MVREF_CA_DIMMB_R 12
D02
MRT Test Fail
Gary
D01A_1015_Alex
R530
R530
1K_1%_04
1K_1%_04
3,5,9,10,12,13,14,15,16,17,18,19,20,21,22,24,25,26,27,28,29,30,32,33,34,35,36,37,41,44,46,61
3.3VS
3,4,6,9,10,12,30,39
VDDQ
9,10,12,39
VTT_MEM
C546
C546
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
1u_6.3V_X5R_04
1u_6.3V_X5R_04
Title
Title
Title
[11] DDR3 SO-DIMM_1
[11] DDR3 SO-DIMM_1
[11] DDR3 SO-DIMM_1
Size
Size
Size
Document Number
Document Number
Document Number
6-71-P15S0-DA3A
6-71-P15S0-DA3A
6-71-P15S0-DA3A
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date:
Date:
Date:
Thursday, March 06, 2014
Thursday, March 06, 2014
Thursday, March 06, 2014
Sheet
Sheet
Sheet
11
11
11
2
1
D
C
B
A
Rev
Rev
Rev
1.0
1.0
1.0
of
of
of
66
66
66
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