Table of Contents
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Processor 3/7
5
U32C
U32C
Haswell rPGA EDS
Haswell rPGA EDS
9,10
M_A_DQ[63:0]
M_A_DQ0
AR15
SA_DQ_0
M_A_DQ1
AT14
D
SA_DQ_1
M_A_DQ2
AM14
SA_DQ_2
M_A_DQ3
AN14
SA_DQ_3
AT15
M_A_DQ4
SA_DQ_4
M_A_DQ5
AR14
SA_DQ_5
M_A_DQ6
AN15
SA_DQ_6
M_A_DQ7
AM15
SA_DQ_7
M_A_DQ8
AM9
SA_DQ_8
M_A_DQ9
AN9
SA_DQ_9
AM8
M_A_DQ10
SA_DQ_10
M_A_DQ11
AN8
SA_DQ_11
M_A_DQ12
AR9
SA_DQ_12
M_A_DQ13
AT9
SA_DQ_13
M_A_DQ14
AR8
SA_DQ_14
M_A_DQ15
AT8
SA_DQ_15
AJ9
M_A_DQ16
SA_DQ_16
M_A_DQ17
AK9
SA_DQ_17
M_A_DQ18
AJ6
SA_DQ_18
M_A_DQ19
AK6
SA_DQ_19
M_A_DQ20
AJ10
SA_DQ_20
M_A_DQ21
AK10
SA_DQ_21
AJ7
M_A_DQ22
SA_DQ_22
M_A_DQ23
AK7
SA_DQ_23
M_A_DQ24
AF4
SA_DQ_24
M_A_DQ25
AF5
SA_DQ_25
M_A_DQ26
AF1
SA_DQ_26
M_A_DQ27
AF2
SA_DQ_27
AG4
M_A_DQ28
SA_DQ_28
M_A_DQ29
AG5
SA_DQ_29
C
M_A_DQ30
AG1
SA_DQ_30
M_A_DQ31
AG2
SA_DQ_31
M_A_DQ32
J1
SA_DQ_32
M_A_DQ33
J2
SA_DQ_33
J5
M_A_DQ34
SA_DQ_34
M_A_DQ35
H5
SA_DQ_35
M_A_DQ36
H2
SA_DQ_36
M_A_DQ37
H1
SA_DQ_37
M_A_DQ38
J4
SA_DQ_38
M_A_DQ39
H4
SA_DQ_39
F2
M_A_DQ40
SA_DQ_40
M_A_DQ41
F1
SA_DQ_41
M_A_DQ42
D2
SA_DQ_42
M_A_DQ43
D3
SA_DQ_43
M_A_DQ44
D1
SA_DQ_44
M_A_DQ45
F3
SA_DQ_45
M_A_DQ46
C3
SA_DQ_46
M_A_DQ47
B3
SA_DQ_47
M_A_DQ48
B5
SA_DQ_48
M_A_DQ49
E6
SA_DQ_49
M_A_DQ50
A5
SA_DQ_50
D6
M_A_DQ51
SA_DQ_51
M_A_DQ52
D5
SA_DQ_52
M_A_DQ53
E5
SA_DQ_53
M_A_DQ54
B6
SA_DQ_54
M_A_DQ55
A6
SA_DQ_55
M_A_DQ56
E12
SA_DQ_56
D12
M_A_DQ57
SA_DQ_57
M_A_DQ58
B11
B
SA_DQ_58
M_A_DQ59
A11
SA_DQ_59
M_A_DQ60
E11
SA_DQ_60
M_A_DQ61
D11
SA_DQ_61
M_A_DQ62
B12
SA_DQ_62
A12
M_A_DQ63
SA_DQ_63
SM_VREF
AM3
SM_VREF
SA_DIMM_VREFDQ
F16
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
F13
SB_DIMM_VREFDQ
3 OF 9
3 OF 9
All VREF traces should be at least 20 mils wide
and 20 mils spacing to other singals/planes
VDDQ
R442
R442
1K_1%_04
1K_1%_04
R430
R430
0_04
0_04
A
SA_DIMM_VREFDQ
S
D
MVREF_DQ_DIMMA
MVREF_DQ_DIMMA 9,10
R431
R431
*1K_04
*1K_04
Q37
Q37
R429
R429
*AO3402L
*AO3402L
1K_1%_04
1K_1%_04
5
4
3
Haswell Processor 3/7 ( DDR3L )
11,12
M_B_DQ[63:0]
AC7
RSVD_AC7
RSVD
U4
M_A_CLK_DDR#0
SA_CKN0
M_A_CLK_DDR#0 9
V4
M_A_CLK_DDR0
SA_CKP0
M_A_CLK_DDR0 9
AD9
M_A_CKE0
M_A_CKE0 9
SA_CKE_0
U3
M_A_CLK_DDR#1
M_A_CLK_DDR#1 9
SA_CKN1
V3
M_A_CLK_DDR1
M_A_CLK_DDR1 9
SA_CKP1
AC9
M_A_CKE1
SA_CKE_1
M_A_CKE1 9
U2
M_A_CLK_DDR#2
SA_CKN2
M_A_CLK_DDR#2 10
V2
M_A_CLK_DDR2
M_A_CLK_DDR2 10
SA_CKP2
AD8
M_A_CKE2
M_A_CKE2 10
SA_CKE_2
U1
M_A_CLK_DDR#3
M_A_CLK_DDR#3 10
SA_CKN3
V1
M_A_CLK_DDR3
M_A_CLK_DDR3 10
SA_CKP3
AC8
M_A_CKE3
SA_CKE_3
M_A_CKE3 10
M7
M_A_CS#0
M_A_CS#0 9
SA_CS_N_0
L9
M_A_CS#1
M_A_CS#1 9
SA_CS_N_1
M9
M_A_CS#2
M_A_CS#2 10
SA_CS_N_2
M10
M_A_CS#3
M_A_CS#3 10
SA_CS_N_3
M8
M_A_ODT0
SA_ODT_0
M_A_ODT0 9
L7
M_A_ODT1
SA_ODT_1
M_A_ODT1 9
L8
M_A_ODT2
M_A_ODT2 10
SA_ODT_2
L10
M_A_ODT3
M_A_ODT3 10
SA_ODT_3
V5
M_A_BS0
M_A_BS0 9,10
SA_BS_0
U5
M_A_BS1
M_A_BS1 9,10
SA_BS_1
AD1
M_A_BS2
SA_BS_2
M_A_BS2 9,10
V10
VSS
U6
M_A_RAS#
M_A_RAS# 9,10
SA_RAS
U7
M_A_W E#
M_A_W E# 9,10
SA_WE
U8
M_A_CAS#
M_A_CAS# 9,10
SA_CAS
M_A_A[15:0] 9,10
V8
M_A_A0
SA_MA_0
AC6
M_A_A1
SA_MA_1
V9
M_A_A2
SA_MA_2
U9
M_A_A3
SA_MA_3
AC5
M_A_A4
SA_MA_4
AC4
M_A_A5
SA_MA_5
AD6
M_A_A6
SA_MA_6
AC3
M_A_A7
SA_MA_7
AD5
M_A_A8
SA_MA_8
AC2
M_A_A9
SA_MA_9
V6
M_A_A10
SA_MA_10
AC1
M_A_A11
SA_MA_11
AD4
M_A_A12
SA_MA_12
V7
M_A_A13
SA_MA_13
AD3
M_A_A14
SA_MA_14
AD2
M_A_A15
SA_MA_15
M_A_DQS#[7:0] 9,10
AP15
M_A_DQS#0
SA_DQS_N_0
AP8
M_A_DQS#1
SA_DQS_N_1
AJ8
M_A_DQS#2
SA_DQS_N_2
AF3
M_A_DQS#3
SA_DQS_N_3
J3
M_A_DQS#4
SA_DQS_N_4
E2
M_A_DQS#5
SA_DQS_N_5
C5
M_A_DQS#6
SA_DQS_N_6
C11
M_A_DQS#7
SA_DQS_N_7
M_A_DQS[7:0] 9,10
AP14
M_A_DQS0
SA_DQS_P_0
AP9
M_A_DQS1
SA_DQS_P_1
AK8
M_A_DQS2
SA_DQS_P_2
AG3
M_A_DQS3
SA_DQS_P_3
H3
M_A_DQS4
SA_DQS_P_4
E3
M_A_DQS5
SA_DQS_P_5
C6
M_A_DQS6
SA_DQS_P_6
C12
M_A_DQS7
SA_DQS_P_7
DIMM
VDDQ
R482
R482
1K_1%_04
1K_1%_04
R443
R443
0_04
0_04
SB_DIMM_VREFDQ
S
D
MVREF_DQ_DIMMB
MVREF_DQ_DIMMB 11,12
R495
R495
R416
R416
*1K_04
*1K_04
Q56
Q56
R446
R446
*AO3402L
*AO3402L
1K_1%_04
1K_1%_04
SM_VREF
S
DRAMRST_CNTRL
4
3
2
U32D
U32D
Haswell rPGA EDS
Haswell rPGA EDS
M_B_DQ0
AR18
AG8
RSVD_AG8
SB_DQ_0
RSVD
M_B_DQ1
AT18
Y4
M_B_CLK_DDR#0
SB_DQ_1
SB_CKN0
M_B_DQ2
AM17
AA4
M_B_CLK_DDR0
SB_DQ_2
SB_CKP0
AM18
AF10
M_B_DQ3
M_B_CKE0
SB_DQ_3
SB_CKE_0
M_B_DQ4
AR17
Y3
M_B_CLK_DDR#1
SB_DQ_4
SB_CKN1
M_B_DQ5
AT17
AA3
M_B_CLK_DDR1
SB_DQ_5
SB_CKP1
M_B_DQ6
AN17
AG10
M_B_CKE1
SB_DQ_6
SB_CKE_1
M_B_DQ7
AN18
Y2
M_B_CLK_DDR#2
SB_DQ_7
SB_CKN2
M_B_DQ8
AT12
AA2
M_B_CLK_DDR2
SB_DQ_8
SB_CKP2
AR12
AG9
M_B_DQ9
M_B_CKE2
SB_DQ_9
SB_CKE_2
M_B_DQ10
AN12
Y1
M_B_CLK_DDR#3
SB_DQ_10
SB_CKN3
M_B_DQ11
AM11
AA1
M_B_CLK_DDR3
SB_DQ_11
SB_CKP3
M_B_DQ12
AT11
AF9
M_B_CKE3
SB_DQ_12
SB_CKE_3
M_B_DQ13
AR11
SB_DQ_13
M_B_DQ14
AM12
P4
M_B_CS#0
SB_DQ_14
SB_CS_N_0
AN11
R2
M_B_DQ15
M_B_CS#1
SB_DQ_15
SB_CS_N_1
M_B_DQ16
AR5
P3
M_B_CS#2
SB_DQ_16
SB_CS_N_2
M_B_DQ17
AR6
P1
M_B_CS#3
SB_DQ_17
SB_CS_N_3
M_B_DQ18
AM5
SB_DQ_18
M_B_DQ19
AM6
R4
M_B_ODT0
SB_DQ_19
SB_ODT_0
M_B_DQ20
AT5
R3
M_B_ODT1
SB_DQ_20
SB_ODT_1
AT6
R1
M_B_DQ21
M_B_ODT2
SB_DQ_21
SB_ODT_2
M_B_DQ22
AN5
P2
M_B_ODT3
SB_DQ_22
SB_ODT_3
M_B_DQ23
AN6
R7
M_B_BS0
SB_DQ_23
SB_BS_0
M_B_DQ24
AJ4
P8
M_B_BS1
SB_DQ_24
SB_BS_1
M_B_DQ25
AK4
AA9
M_B_BS2
SB_DQ_25
SB_BS_2
M_B_DQ26
AJ1
SB_DQ_26
AJ2
R10
M_B_DQ27
SB_DQ_27
VSS
M_B_DQ28
AM1
R6
M_B_RAS#
SB_DQ_28
SB_RAS
M_B_DQ29
AN1
P6
M_B_W E#
SB_DQ_29
SB_WE
M_B_DQ30
AK2
P7
M_B_CAS#
SB_DQ_30
SB_CAS
M_B_DQ31
AK1
SB_DQ_31
M_B_DQ32
L2
R8
M_B_B0
SB_DQ_32
SB_MA_0
M2
Y5
M_B_DQ33
M_B_B1
SB_DQ_33
SB_MA_1
M_B_DQ34
L4
Y10
M_B_B2
SB_DQ_34
SB_MA_2
M_B_DQ35
M4
AA5
M_B_B3
SB_DQ_35
SB_MA_3
M_B_DQ36
L1
Y7
M_B_B4
SB_DQ_36
SB_MA_4
M_B_DQ37
M1
AA6
M_B_B5
SB_DQ_37
SB_MA_5
M_B_DQ38
L5
Y6
M_B_B6
SB_DQ_38
SB_MA_6
M5
AA7
M_B_DQ39
M_B_B7
SB_DQ_39
SB_MA_7
M_B_DQ40
G7
Y8
M_B_B8
SB_DQ_40
SB_MA_8
M_B_DQ41
J8
AA10
M_B_B9
SB_DQ_41
SB_MA_9
M_B_DQ42
G8
R9
M_B_B10
SB_DQ_42
SB_MA_10
M_B_DQ43
G9
Y9
M_B_B11
SB_DQ_43
SB_MA_11
M_B_DQ44
J7
AF7
M_B_B12
SB_DQ_44
SB_MA_12
M_B_DQ45
J9
P9
M_B_B13
SB_DQ_45
SB_MA_13
M_B_DQ46
G10
AA8
M_B_B14
SB_DQ_46
SB_MA_14
M_B_DQ47
J10
AG7
M_B_B15
SB_DQ_47
SB_MA_15
M_B_DQ48
A8
SB_DQ_48
M_B_DQ49
B8
SB_DQ_49
A9
AP18
M_B_DQ50
M_B_DQS#0
SB_DQ_50
SB_DQS_N_0
M_B_DQ51
B9
AP11
M_B_DQS#1
SB_DQ_51
SB_DQS_N_1
M_B_DQ52
D8
AP5
M_B_DQS#2
SB_DQ_52
SB_DQS_N_2
M_B_DQ53
E8
AJ3
M_B_DQS#3
SB_DQ_53
SB_DQS_N_3
M_B_DQ54
D9
L3
M_B_DQS#4
SB_DQ_54
SB_DQS_N_4
M_B_DQ55
E9
H9
M_B_DQS#5
SB_DQ_55
SB_DQS_N_5
E15
C8
M_B_DQ56
M_B_DQS#6
SB_DQ_56
SB_DQS_N_6
M_B_DQ57
D15
C14
M_B_DQS#7
SB_DQ_57
SB_DQS_N_7
M_B_DQ58
A15
AP17
M_B_DQS0
SB_DQ_58
SB_DQS_P_0
M_B_DQ59
B15
AP12
M_B_DQS1
SB_DQ_59
SB_DQS_P_1
M_B_DQ60
E14
AP6
M_B_DQS2
SB_DQ_60
SB_DQS_P_2
M_B_DQ61
D14
AK3
M_B_DQS3
SB_DQ_61
SB_DQS_P_3
A14
M3
M_B_DQ62
M_B_DQS4
SB_DQ_62
SB_DQS_P_4
M_B_DQ63
B14
H8
M_B_DQS5
SB_DQ_63
SB_DQS_P_5
C9
M_B_DQS6
SB_DQS_P_6
C15
M_B_DQS7
SB_DQS_P_7
4 OF 9
4 OF 9
VDDQ
R698
R698
0_04
0_04
1K_1%_04
1K_1%_04
D
SM_VREF_R
SM_VREF_R 9,11
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
R699
R699
Q36
Q36
*AO3402L
*AO3402L
1K_1%_04
1K_1%_04
Title
Title
Title
[04] PROCESSOR 3/7
[04] PROCESSOR 3/7
[04] PROCESSOR 3/7
Size
Size
Size
Document Number
Document Number
Document Number
6-71-P15S0-DA3A
6-71-P15S0-DA3A
6-71-P15S0-DA3A
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
DRAMRST_CNTRL 3,20
Date:
Date:
Date:
Thursday, March 06, 2014
Thursday, March 06, 2014
Thursday, March 06, 2014
2
Schematic Diagrams
1
D
M_B_CLK_DDR#0 12
M_B_CLK_DDR0 12
M_B_CKE0 12
M_B_CLK_DDR#1 12
M_B_CLK_DDR1 12
M_B_CKE1 12
M_B_CLK_DDR#2 11
M_B_CLK_DDR2 11
M_B_CKE2 11
M_B_CLK_DDR#3 11
M_B_CLK_DDR3 11
M_B_CKE3 11
M_B_CS#0 12
M_B_CS#1 12
M_B_CS#2 11
M_B_CS#3 11
M_B_ODT0 12
M_B_ODT1 12
M_B_ODT2 11
M_B_ODT3 11
M_B_BS0 11,12
Sheet 4 of 66
M_B_BS1 11,12
M_B_BS2 11,12
Processor 3/7
M_B_RAS# 11,12
C
M_B_W E# 11,12
M_B_CAS# 11,12
M_B_B[15:0] 11,12
M_B_DQS#[7:0] 11,12
M_B_DQS[7:0] 11,12
B
3,6,9,10,11,12,30,39
VDDQ
A
Rev
Rev
Rev
1.0
1.0
1.0
Sheet
Sheet
Sheet
4
4
4
of
of
of
66
66
66
1
Processor 3/7 B - 5
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