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Schematic Diagrams
PS8625
D
d
Sheet 11 of 45
PS8625
C
B
A
B - 12 PS8625
5
4
3.3VS
3.3VS
L7
VDDIO
L35
HCB1005KF-121T20
HCB1005KF-121T20
VDDIOX
C32
C33
C310
C309
0.47u_10V_Y5V_04
1u_6.3V_X5R_04
0.47u_10V_Y5V_04
4.7u_6.3V_X5R_06
8625_GNDA
W
>
^t Khd W
W
W
d
^t Khd
d
'Ey
W
W
W
'E
W^
'E
'E
'E
'E
W
W
&
s/Ky
s/Ky
d
'E
&
s/Ky
'E
&
/
W
>
s/Ky
W^
JP1
*28mil_06
W
8625_GNDA
Note:
The decoupling caps C9, C15, C16, C17, C18, C21
eDP, R288 un-mount
shall be close to the power pins as possible
R288
1K_04
HPD
12,6
EDP_HPD
eDP,C303,C304 un-mount
C303
0.1u_10V_X7R_04
DAUXn
6
DP_AUXN
DAUXp
C304
0.1u_10V_X7R_04
6
DP_AUXP
C38
eDP,C305,C306 un-mount
0.1u_16V_Y5V_04
C305
0.1u_10V_X7R_04
DRX0p
6
EDP_TXP_0
C306
0.1u_10V_X7R_04
DRX0n
6
EDP_TXN_0
8625_GNDA
eDP,C307,C308 un-mount
C307
0.1u_10V_X7R_04
DRX1p
6
EDP_TXP_1
DRX1n
C308
0.1u_10V_X7R_04
6
EDP_TXN_1
R475
0_04
17
L_BRIGHTNESS_R
PWM_IN
R476
*0_04
30
BRIGHTNESS
R277
*100K_04
Power On Configuration
GND
R284 *4.7K_04
RLV_CFG
R283
4.7K_04
VDDIO
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K
L: 8-bit LVDS, VESA mapping
M: 8-bit LVDS, JEIDA mapping
VDDIO
H: 6-bit LVDS, both VESA and JEIDA mapping
R31
*4.7K_04
RLV_LNK/GPIO0
R29
*4.7K_04
30
SMC_EDP_CLK
30
SMD_EDP_DAT
8625_GNDA
RLV_LNK: LVDS single link or dual link selection, internal pull-down ~80K
L: Single link LVDS
H: Dual link LVDS
RTD_PLVDD_EN
R27
*4.7K_04
VDDIO
I2C_ADDR: I2C Slave address selection, internal pull-down ~80K
L: 0x10h~0x1Fh
H: 0x90h~0x9Fh
5
4
3
L33
L34
BCNR3010C-2R2M
HCB1005KF-121T20
SW_OUT
1
2
VDD12
VDDRX
R286
10K_04
C299
C39
C41
4.7u_6.3V_X5R_06
*4.7u_6.3V_X5R_06
1u_6.3V_X5R_04
C312
1u_6.3V_X5R_04
8625_GNDA
'E
'E
VDDIO
C37
0.1u_16V_Y5V_04
8625_GNDA
U15
DAUXn
1
42
LVDS-U0N
DAUXn
TA1n
DAUXp
2
41
LVDS-U0P
DAUXp
TA1p
3
40
LVDS-U1N
8625_GNDA
GND
TB1n
DRX0p
4
39
LVDS-U1P
DRX0p
TB1p
DRX0n
5
38
DRX0n
VDDIO
VDDRX
6
37
LVDS-U2N
VDDRX
TC1n
DRX1p
7
36
LVDS-U2P
PS8625
DRX1p
TC1p
DRX1n
8
35
LVDS-UCLKN
DRX1n
TCK1n
C40
RST#
9
34
LVDS-UCLKP
RST#
TCK1p
PD#
10
33
RTD_PLVDD_EN
PD#
ENPVCC/I2C_ADDR
0.01u_16V_X7R_04
HPD
11
32
HPD
TD1n
PANEL_PWM
12
31
PWMO
TD1p
VDDIOX
13
30
P_DDC_DATA
VDDIOX
DDC_SDA
P_DDC_CLK
VDDIOX
14
29
VDDIOX
DDC_SCL
57
8625_GNDA
Epad
6-03-08625-030
C36
C35
Noe:
R13: LVDS output swing control
4.99K for default swing, change the value for swing adjust
3.3VS
8625_GNDA
8625_GNDA
/
WZKD
SMC_EDP_CLK
SMD_EDP_DAT
I2C_CFG = "H"
EEPROM for Initial Code
I2C Address: 0xA0
Suggest minimum 2Kbit
10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,3,30,31,35,6,9
3
2
1
PWM_IN
R474
*0_04
PANEL_PWM
R285
10K_04
RTD_PLVDD_EN
RTD_PLVDD_EN
12
ENBLT
ENBLT
12
C311
PANEL_PWM
PANEL_PWM
12
2.2u_6.3V_X5R_04
LVDS-L0N
LVDS-L0N
12
LVDS-L0P
LVDS-L0P
12
LVDS-L1N
LVDS-L1N
12
LVDS-L1P
Single link
LVDS-L1P
12
LVDS
LVDS-L2N
LVDS-L2N
12
LVDS-L2P
LVDS-L2P
12
LVDS-LCLKN
LVDS-LCLKN
12
LVDS-LCLKP
LVDS-LCLKP
12
LVDS-U0N
LVDS-U0N
12
LVDS-U0P
LVDS-U0P
12
LVDS-U1N
LVDS-U1N
12
LVDS-U1P
LVDS-U1P
12
LVDS-U2N
LVDS-U2N
12
LVDS-U2P
LVDS-U2P
12
LVDS-UCLKN
LVDS-UCLKN
12
LVDS-UCLKP
LVDS-UCLKP
12
VDDIO
P_DDC_CLK
P_DDC_CLK
12
P_DDC_DATA
P_DDC_DATA
12
C34
0.1u_16V_Y5V_04
8625_GNDA
To LVDS Connector
eDP, R289,R290,R291,R292,R293,R294 mount
DP_AUXN
R289
*0_04
DP_AUX#
DP_AUX#
12
DP_AUXP
R290
*0_04
DP_AUX
DP_AUX
12
EDP_TXN_0
DP_TXN0
R292
*0_04
DP_TXN0
12
EDP_TXP_0
R291
*0_04
DP_TXP0
DP_TXP0
12
EDP_TXN_1
DP_TXN1
R294
*0_04
DP_TXN1
12
EDP_TXP_1
R293
*0_04
DP_TXP1
DP_TXP1
12
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[11] PS8625(EDP TO LVDS)
[11] PS8625(EDP TO LVDS)
[11] PS8625(EDP TO LVDS)
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W54S0-D02A
6-71-W54S0-D02A
6-71-W54S0-D02A
3.3VS
Custom
Custom
Custom
6-7P-W5409-002
6-7P-W5409-002
6-7P-W5409-002
Date:
Date:
Date:
Wednesday, September 25, 2013
Wednesday, September 25, 2013
Wednesday, September 25, 2013
Sheet
Sheet
Sheet
11
11
11
o f
o f
o f
2
1
D
Dual link
LVDS
C
B
A
R e v
R e v
R e v
2.0A
2.0A
2.0A
45
45
45
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