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Schematic Diagrams
Power on / S4 Resume Seq.
2
3
3a
3b
4
5
D
6
6a
6b
7
7a
7b
7c
7d
Sheet 63 of 66
7e
7e
Power on /
C
7f
S4 Resume Seq.
9
10
11
12
13a
13b
14
14
15
16
16b
16c
B
16a
16a
17
A
B - 64 Power on / S4 Resume Seq.
5
4
PWR_SW#
636ms
140.8ms
DD_ON
3.3V
1.768ms
5V
2.44ms
RSMRST#
PWR_BTN#
176ms
124ms
SUSC#
190ms
VDDQ
6.72ms
V_VCCDDQ
6.72ms
SUSB#
7
34us
SUSB#
5VS
7a
640us
5VS
3.3VS
7b
1.12ms
3.3VS
1.5VS
7c
1.66ms
1.5VS
7d
1.05V_LAN_M
1.05V_LAN_M
1.176ms
7e
1.05VM
1.2ms
1.05VM
7e
1.232ms
1.05VS
1.05VS
VTT_MEM
VTT_MEM
7f
1.08ms
ALL_SYS_PWRGD
9
ALL_SYS_PWRGD
6.68ms
10
PM_PCH_PWROK
PM_PCH_PWROK
2.8ms
PMSYS_PWRGD_BUF
11
PMSYS_PWRGD_BUF
56ms
H_CPUPWRGD
12
H_CPUPWRGD
62.8ms
VCORE
13a
VCORE
8.26ms
DELAY_PWRGD
13b
DELAY_PWRGD
8.32ms
228ms+37.2ns
SYS_PWROK
SYS_PWROK
14
228ms
14
PCH_PWROK_EC
PCH_PWROK_EC
229.24ms+37.2ns
PLT_RST#
15
PLT_RST#
dGPU_PWR_EN#
16
dGPU_PWR_EN#
148ms
3V3_RUN
156ms
16b
3V3_RUN
5V_RUN
156.6ms
16c
5V_RUN
PWR_SRC
157.008ms
16a
PWR_SRC
DGPU_PWRGD
4.5ms
102ms
MXM_RST#
5
4
3
2
PWR_SW#
3
DD_ON
3a
3.3V
3b
5V
4
RSMRST#
5
PWR_BTN#
6
SUSC#
6a
VDDQ
6b
V_VCCDDQ
16a
DGPU_PWRGD
17
MXM_RST#
3
2
1
D
C
B
A
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[63] POWER ON/S4 RESUME SEQ.
[63] POWER ON/S4 RESUME SEQ.
[63] POWER ON/S4 RESUME SEQ.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
6-71-P15S0-DA1
6-71-P15S0-DA1
6-71-P15S0-DA1
2.0
2.0
2.0
C
C
C
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date:
Date:
Date:
Thursday, March 06, 2014
Thursday, March 06, 2014
Thursday, March 06, 2014
Sheet
Sheet
Sheet
63
63
63
of
of
of
66
66
66
2
1
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