Ps8625 - Clevo P177SM Service Manual

Schematic Diagrams

PS8625

14 iGP_eDP_AUX#_R
14 iGP_eDP_AUX_R
Sheet 15 of 60
PS8625
14 eDP_TX0_R
14 eDP_TX#0_R
14 eDP_TX1_R
14 eDP_TX#1_R
CPU EDP BRIGHTNESS
5 EDP_DISP_UTIL
Power On Configuration
D01a_1009_Alex
R175
GND
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K
L: 8-bit LVDS, VESA mapping
M: 8-bit LVDS, JEIDA mapping
H: 6-bit LVDS, both VESA and J EIDA mapping
RLV_LNK/GPIO0
RLV_LNK: LVDS single link or dual link selection, internal pull-down ~80K
L: Single link LVDS
H: Dual link LVDS
ENPVCC
I2C_ADDR: I2C Slav e address selec tion, internal pull-down ~80K
L: 0x10h~0x1Fh
H: 0x90h~0x9Fh
B - 16 PS8625
L56 L55
HCB1005KF-121T20 HCB1005KF-121T20
3.3V VDDIO 3.3V
C170 C533
C169 C438
Switching Regulator Layout Guideline
1. Place the switching regulator inductor (L3) close to SW_OUT Pins (Pin15, Pin16).
2. The SW_OUT output traces should be as wide as possible.
3. The GNDX pins (Pin17, Pin18) should be connected to the main PCB ground plane, with the device GND pins of the PS8625 connected to separate GND island (GNDA) for the device.
The GND island (GNDA) should be connected to the main GND plane (GND) with a single-point connection by use of a wide PCB trace.
R155 0_04
DAUXn
4. Place the 4.7uF decoupling Capacitor (C4) for VDDIOX close to VDDIOX pin.
R160 0_04
DAUXp
5. The GND of the 4.7uF capacitor (C4) for VDDIOX should be placed close to the GND of 4.7uF capacitor (C5) behind Inductor.
6. Place the bead (L2) for VDDIOX close to PS8625.
R145 0_04
C51 0.1u_10V_X7R_04 DRX0p
R147 0_04
C60 0.1u_10V_X7R_04 DRX0n
R149 0_04
C63 0.1u_10V_X7R_04 DRX1p
R154 0_04
DRX1n
C66 0.1u_10V_X7R_04
R174 *0_04
R179 0_04
D01A_1016_Alex
22 L_BRIGHTNESS_R
R172 *0_04 D02_1116_Alex
PWMI
34 BRIGHTNESS
EC BRIGHTNESS
R121
100K_04
R97 1K_04
PS_HPD
5,14 iGP_eDP_HPD
R115
*100K_04
*4.7K_04 R176 4.7K_04
RLV_CFG VDDIO
R177 4.7K_04
VDDIO
R178 *4.7K_04
VDDIO
BCIHP0420TB-2R2M L68
HCB1005KF-121T20
VDDIOX SW_OUT L74 VDD12 VDDRX
C534 C195
PGND
VDDIO
R805 D01a_1009_Alex
GND GNDA
*15mil_short_06
single PCB trace
U65
Note:
The decoupling caps C9, C15, C16, C17, C18, C21
shall be close to the power pins as possible
1
DAUXn
DAUXn TA1n
2
DAUXp
DAUXp TA1p
GNDA 3
GND TB1n
DRX0p 4
DRX0p TB1p
DRX0n 5
DRX0n VDDIO
VDDRX 6
VDDRX TC1n
DRX1p 7
PS8625
DRX1p TC1p
8
DRX1n
DRX1n TCK1n
9
RST#
RST# TCK1p
PD# 10
C198 C197
PD# ENPVCC/I2C_ADDR
PS_HPD 11
HPD TD1n
PWMO 12
PWMO TD1p
VDDIOX 13
14 VDDIOX DDC_SDA
VDDIOX
VDDIOX DDC_SCL
57
GNDA
Epad
Noe:
R13: LVDS output swing control
C231 C233
4.99K f or def ault s wing, change the v alue f or swing adjust
13,34
13,34
3.3V 2,3,14,19,29,30,32,36,37,39,41,42,62
ENPVCC
PS_PANEL_EN 14
ENBLT
PS_BKL_EN 14
PWMO
PWMO 14
LVDS_U0N
LVDS_U0N 14
LVDS_U0P
LVDS_U0P 14
C267 LVDS_U1N
LVDS_U1N 14
LVDS_U1P
LVDS_U1P 14
LVDS_U2N
LVDS_U2N 14
LVDS_U2P
LVDS_U2P 14
LVDS_UCLKN
LVDS_UCLKN 14
LVDS_UCLKP
LVDS_UCLKP 14
TD0n
TD0p
LVDS_L0N
LVDS_L0N 14
LVDS_L0P
LVDS_L0P 14
LVDS_L1N
LVDS_L1N 14
LVDS_L1P
LVDS_L1P 14
LVDS_L2N
LVDS_L2N 14
LVDS_L2P
LVDS_L2P 14
LVDS_LCLKN
LVDS_LCLKN 14
LVDS_LCLKP
LVDS_LCLKP 14
TD1n
TD1p
VDDIO
D01a_1009_Alex
42
LVDS_U0N
41
LVDS_U0P
40 LVDS_U1N
39 LVDS_U1P
38 VDDIO
37 LVDS_U2N C270
36 LVDS_U2P
35
LVDS_UCLKN
34
LVDS_UCLKP
33 ENPVCC
32 TD1n
31 TD1p
30 DDC_SDA
LVDS_DDC_DAT 14
29
DDC_SCL
LVDS_DDC_CLK 14
VDDIO
D01A_1016_Alex
Initial Code EEPROM
VDDIO
R150 0_04 RLV_LNK/GPIO0
CSCL/MSCL
SMC_VGA_THERM
CSDA/MSDA
SMD_VGA_THERM
R165 0_04
I2C_CFG = "H"
EEPROM f or Initial Code
I2C Address: 0xA0
Sugges t minimum 2Kbit
U77
8 1
7 VCC E0 2
WC# E1
6 3
SCL E2
5 4
SDA VSS
*M24C02~M24C16