Silicon Laboratories C8051F55 Series User Manual page 9

5.4. Switches and LEDs (J15, J19)
Two push-button switches are provided on the target board for each MCU. Switch RESET_A is connected to the
RST pin of the C8051F568. Switch RESET_B is connected to the RST pin of the C8051F550. Pressing RESET_A
puts the C8051F568 device into its hardware-reset state, and similarly for RESET_B and the C8051F550 MCU.
Switches P1.4_A and P1.4_B are connected to the MCU's general purpose I/O (GPIO) pins through headers.
Pressing either one of these switches generates a logic low signal on the port pin. Remove the shorting block from
the header to disconnect these switches from the port pins. See Table 1 for the port pins and headers
corresponding to each switch.
Four LEDs are provided on the target board to serve as indicators. The red LED labeled PWR LED indicates
presence of power to the target board. The second red LED labeled COMM indicates if the CP2102 USB-to-UART
bridge is recognized by the PC. The green LED on Side A is labeled with a port pin name and is connected to a
C8051F568 GPIO pin through a header. Remove the shorting block from the header to disconnect the LED from
the port pin. Similarly, a second green LED on Side B is connected to the C8051F550 through another header. See
Table 1 for the port pins and headers corresponding to each LED.
5.5. Target Board Debug Interfaces (P2 and P3)
The debug connectors P2 (DEBUG_A) and P3 (DEBUG_B) provide access to the debug (C2) pins of the
C8051F568 and C8051F550. The debug connectors are used to connect the Serial Adapter or the USB Debug
Adapter to the target board for in-circuit debugging and Flash programming. Table 2 shows the DEBUG pin
definitions.
Side A - C8051F568
Pin #
1
2, 3, 9
4
5
6
7
8
10 USB Power (+5VDC from P2)
Table 1. Target Board I/O Descriptions
Description
RESET_A
RESET_B
P1.4_A Switch
P1.4_B Switch
P1.3_A LED
P1.3_B LED
Red LED (PWR)
Red LED (COMM)
Table 2. DEBUG Connector Pin Descriptions
Description
Not Connected
GND (Ground)
P4.0_C2D_A
RST_A (Reset)
P4.0_A
RST/C2CK_A
Not Connected
C8 05 1 F 5 5x /5 6x / 57 x
I/O Header(s)
Reset (Side A)
Reset (Side B)
P1.4 (Side A)
P1.4 (Side B)
P1.3 (Side A)
P1.3 (Side B)
Power
COMM Active
Side B - C8051F550
Pin #
1
2, 3, 9
4
5
6
7
8
10
Rev. 0.2
none
none
J19[1–2]
J15[1–2]
J19[3–4]
J15[3–4]
none
none
Description
Not Connected
GND (Ground)
P2.1_C2D_B
RST_B (Reset)
P2.1_B
RST/C2CK_B
Not Connected
Not Connected
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