Silicon Laboratories C8051F55 Series User Manual page 11

5.8. LIN Interface and Network (J12, J17, J21, TB1)
Both MCUs on the target board are connected to LIN transceivers through headers. These headers assume that
the MCU's crossbars are configured to put the LIN TX and RX pins on port pins P1.0 and P1.1 respectively. See
the C8051F55x/56x/57x data sheet for crossbar configuration. The C8051F568 (Side A) is connected to the T1
transceiver through the J17 header and the C8051F550 (Side B) is connected to the T2 transceiver through the
J12 header. The two LIN transceivers are connected to each other and form a LIN network. Other external devices
can be connected to the LIN network through the TB1 interface. The TB1 interface also provides the option for
connecting an external power source so that all LIN transceivers can use the same source voltage. This source
voltage can also be used to power the target board. If an external voltage source is not provided, the LIN
transceivers use the 12V provided through the P4 power adapter connector. See Section 5.2. for more power
option details. The shorting block positions for connecting the MCUs to the LIN transceivers are listed in Table 6.
The pin connections for the external LIN devices are listed in Table 7.
Table 6. LIN Interface Headers (J12 and J17) Description
Table 7. TB1 External LIN Interface Header Description
Header J21 connects the P4 power-adapter supply to the V_HIGH node, which is used as the power source for the
LIN transceivers (T1, T2). The shorting block on header J21 can be removed to force the LIN transceivers to use
the voltage supply externally supplied on the +LIN_V pin on the TB1 header.
Header Pins LIN0 Pin Description
J17[9–10] LIN_TX (P1.0_A)
J17[11–12] LIN_RX (P1.1_A)
J12[3–4] LIN_TX (P1.0_B)
J12[1–2] LIN_RX (P1.1_B)
Pin # Pin Description
1
2 LIN_OUT
3
Rev. 0.2
C8 05 1 F 5 5x /5 6x / 57 x
GND
+LIN_V
11