Silicon Laboratories C8051F55 Series User Manual page 14

C8 051 F55x / 56x/ 57 x
external memory interface. The output pins of the latch are connected to the 96-pin header and include an _L suffix
in the pin name.
5.12. Potentiometer (J20)
The C8051F568 (Side A) device has the option to connect port pin P1.2 to a 10K linear potentiometer (R27). The
potentiometer is connected through the J20 header. The potentiometer can be used for testing the analog-to-digital
(ADC) converter of the MCU.
5.13. Power Supply I/O (Side A) (TB3)
All of the C8051F568 target device's supply pins are connected to the TB3 terminal block. Refer to Table 11 for the
TB3 terminal block connections.
5.14. Alternate Power Supply Headers (J18, J21)
The C8051F560 Target Board includes two headers that allow for alternate power sources and power
measurement. Header J18 connects the VIO voltage supplied to the Side A MCU to other peripherals on the board,
such as the P1.4_A push-button switch pull-up, and the R27 potentiometer source. To enable current
measurement, the shorting block on J18 can be removed so that the VIO_A node only powers the VIO pin on the
MCU. Another voltage source will need to be applied to the VIO_SRC node to power the other peripherals.
5.15. C2 Pin Sharing
On the C8051F568 (Side A) and the C8051F550 (Side B), the debug pins C2CK and C2D are shared with the pins
RST and P4.0/P2.1 respectively. The target board includes the resistors necessary to enable pin sharing which
allow the pin–shared pins to be used normally while simultaneously debugging the device. See Application Note
"AN124: Pin Sharing Techniques for the C2 Interface" at
sharing.
14
Table 11. TB3 Terminal Block Pin Descriptions
Pin # Description
1
2
3
4
5
6
Rev. 0.2
VIO_A
VREGIN_A
VDD_A
VDDA_A
GNDA_A
GND
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