Silicon Laboratories C8051F55 Series User Manual page 16

C8 051 F55x / 56x/ 57 x
Table 12. C8051F560 Target Board Pin Assignments and Headers (Continued)
MCU Pin Name Pin#
P3.1 17
P3.2 16
P3.3 15
P3.4 14
P3.5 13
P3.6 12
P3.7 11
P4.0_C2D 9
RST/C2CK 10
VIO 2
VREGIN 3
VDD 4
VDDA 5
GND 6
GNDA 7
*Note: Headers denoted by this symbol are not directly connected to the MCU pin; the connection might be via one or more
headers and/or pin-sharing resistor(s). See board schematic for details.
16
Primary Alternate Fixed
Function Function
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
C2D P4.0
RST C2CK
VIO
VREGIN
VDD
VDDA
GND
GNDA
Rev. 0.2
Target Board Relevant Headers
Function
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO P2[4], P2[6]*
RST/C2CK P2[7], P2[5]*
VIO J4[2], J18[1], TB3[1]
J0-J3[9]*, J23
VREGIN J24[2], TB3[2]
VDD
VDDA
GND J0-J3[10], TB3[6]
GNDA
J3[2]
J3[3]
J3[4]
J3[5]
J3[6]
J3[7]
J3[8]
TB3[3]
TB3[4]
TB3[5]