Freescale Semiconductor KV31F Manuals

Freescale Semiconductor KV31F Manuals

Manuals and User Guides for Freescale Semiconductor KV31F. We have 1 Freescale Semiconductor KV31F manual available for free PDF download: Reference Manual

Freescale Semiconductor KV31F Reference Manual

Freescale Semiconductor KV31F Reference Manual (1237 pages)

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Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 8 MB

Table of Contents

Table of Contents
3
About this Document
43
Overview
43
Purpose
43
Audience
43
Conventions
43
Numbering Systems
43
Typographic Notation
44
Special Terms
44
Introduction
45
Overview
45
Module Functional Categories
45
ARM® Cortex®-M4 Core Modules
46
System Modules
47
Memories and Memory Interfaces
47
Clocks
48
Security and Integrity Modules
48
Analog Modules
49
Timer Modules
49
Communication Interfaces
50
Human-Machine Interfaces
51
Orderable Part Numbers
51
Chip Configuration
53
Introduction
53
Core Modules
53
ARM Cortex-M4 Core Configuration
53
Nested Vectored Interrupt Controller (NVIC) Configuration
55
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
61
FPU Configuration
62
JTAG Controller Configuration
62
System Modules
63
SIM Configuration
63
System Mode Controller (SMC) Configuration
64
PMC Configuration
64
Low-Leakage Wake-Up Unit (LLWU) Configuration
65
MCM Configuration
66
Crossbar-Light Switch Configuration
67
Peripheral Bridge Configuration
69
DMA Request Multiplexer Configuration
70
DMA Controller Configuration
73
External Watchdog Monitor (EWM) Configuration
74
Watchdog Configuration
76
Clock Modules
77
MCG Configuration
77
OSC Configuration
79
Memories and Memory Interfaces
79
Flash Memory Configuration
79
Flash Memory Controller Configuration
82
SRAM Configuration
83
System Register File Configuration
84
Ezport Configuration
85
Flexbus Configuration
86
Security
89
CRC Configuration
89
RNG Configuration
90
Analog
91
16-Bit SAR ADC Configuration
91
CMP Configuration
98
12-Bit DAC Configuration
100
VREF Configuration
102
Timers
103
PDB Configuration
103
Flextimer Configuration
106
PIT Configuration
112
Low-Power Timer Configuration
113
Communication Interfaces
115
SPI Configuration
115
I2C Configuration
119
UART Configuration
119
LPUART Configuration
122
Human-Machine Interfaces
122
GPIO Configuration
123
Memory Map
125
Introduction
125
System Memory Map
125
Aliased Bit-Band Regions
127
Flash Access Control Introduction
128
Flash Memory Map
128
Alternate Non-Volatile IRC User Trim Description
129
SRAM Memory Map
129
Peripheral Bridge (AIPS-Lite) Memory Map
130
Read-After-Write Sequence and Required Serialization of Memory Operations
130
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
130
Private Peripheral Bus (PPB) Memory Map
134
Clock Distribution
137
Introduction
137
Programming Model
137
High-Level Device Clocking Diagram
137
Clock Definitions
138
Device Clock Summary
139
Internal Clocking Requirements
141
Clock Divider Values after Reset
143
VLPR Mode Clocking
143
Clock Gating
144
Module Clocks
144
PMC 1-Khz LPO Clock
145
IRC 48Mhz Clock
146
WDOG Clocking
146
Debug Trace Clock
147
PORT Digital Filter Clocking
147
LPTMR Clocking
148
CLKOUT32K Clocking
148
UART Clocking
149
LPUART0 Clocking
149
Reset and Boot
151
Introduction
151
Reset
152
Power-On Reset (POR)
152
System Reset Sources
152
MCU Resets
156
Reset Pin
157
Debug Resets
158
Boot
159
Boot Sources
159
Boot Options
159
FOPT Boot Options
159
Boot Sequence
161
Power Management
163
Introduction
163
Clocking Modes
163
Partial Stop
163
DMA Wakeup
164
Compute Operation
165
Peripheral Doze
166
Clock Gating
167
Power Modes Description
167
Entering and Exiting Power Modes
169
Power Mode Transitions
170
Power Modes Shutdown Sequencing
171
Flash Program Restrictions
172
Module Operation in Low Power Modes
172
Security
177
Introduction
177
Flash Security
177
Security Interactions with Other Modules
178
Security Interactions with Flexbus
178
Security Interactions with Ezport
178
Security Interactions with Debug
178
Introduction
181
References
183
The Debug Port
183
JTAG-To-SWD Change Sequence
184
JTAG-To-Cjtag Change Sequence
184
Debug Port Pin Descriptions
185
System TAP Connection
185
IR Codes
186
JTAG Status and Control Registers
186
MDM-AP Control Register
187
MDM-AP Status Register
189
Debug Resets
190
Ahb-Ap
191
Itm
191
Core Trace Connectivity
192
Tpiu
192
Dwt
192
Debug in Low Power Modes
193
Debug Module State in Low Power Modes
193
Debug & Security
194
Signal Multiplexing and Signal Descriptions
195
Introduction
195
Signal Multiplexing Integration
195
Port Control and Interrupt Module Features
196
Clock Gating
197
Signal Multiplexing Constraints
197
Pinout
197
KV31F Signal Multiplexing and Pin Assignments
197
KV31F Pinouts
201
Module Signal Description Tables
204
Core Modules
204
System Modules
205
Clock Modules
205
Memories and Memory Interfaces
205
Analog
208
Timer Modules
210
Communication Interfaces
211
Human-Machine Interfaces (HMI)
213
Port Control and Interrupts (PORT)
215
Introduction
215
Overview
215
Features
215
Modes of Operation
216
External Signal Description
217
Detailed Signal Description
217
Memory Map and Register Definition
217
Pin Control Register N (Portx_Pcrn)
224
Global Pin Control Low Register (Portx_Gpclr)
226
Global Pin Control High Register (Portx_Gpchr)
227
Interrupt Status Flag Register (Portx_Isfr)
228
Digital Filter Enable Register (Portx_Dfer)
228
Digital Filter Clock Register (Portx_Dfcr)
229
Digital Filter Width Register (Portx_Dfwr)
229
Functional Description
230
Pin Control
230
Global Pin Control
231
External Interrupts
231
Digital Filter
232
System Integration Module (SIM)
235
Introduction
235
Features
235
Memory Map and Register Definition
236
System Options Register 1 (SIM_SOPT1)
237
SOPT1 Configuration Register (SIM_SOPT1CFG)
238
System Options Register 2 (SIM_SOPT2)
239
System Options Register 4 (SIM_SOPT4)
241
System Options Register 5 (SIM_SOPT5)
244
System Options Register 7 (SIM_SOPT7)
245
System Options Register 8 (SIM_SOPT8)
247
System Device Identification Register (SIM_SDID)
249
System Clock Gating Control Register 4 (SIM_SCGC4)
251
System Clock Gating Control Register 5 (SIM_SCGC5)
253
System Clock Gating Control Register 6 (SIM_SCGC6)
255
System Clock Gating Control Register 7 (SIM_SCGC7)
258
System Clock Divider Register 1 (SIM_CLKDIV1)
258
Flash Configuration Register 1 (SIM_FCFG1)
261
Flash Configuration Register 2 (SIM_FCFG2)
263
Unique Identification Register High (SIM_UIDH)
264
Unique Identification Register MID-High (SIM_UIDMH)
264
Unique Identification Register MID Low (SIM_UIDML)
265
Unique Identification Register Low (SIM_UIDL)
265
Functional Description
265
Chip-Specific Information
267
Introduction
267
Functional Description
269
Memory Maps
269
Kinetis Flashloader
269
Start-Up Process
270
Clock Configuration
271
Flashloader Protocol
271
Flashloader Packet Types
275
Flashloader Command API
282
Flashloader Exit State
301
Peripherals Supported
302
I2C Peripheral
302
SPI Peripheral
303
UART Peripheral
305
Get/Setproperty Command Properties
308
Property Definitions
309
Kinetis Flashloader Status Error Codes
311
Reset Control Module (RCM)
313
Introduction
313
Reset Memory Map and Register Descriptions
313
System Reset Status Register 0 (RCM_SRS0)
314
System Reset Status Register 1 (RCM_SRS1)
315
Reset Pin Filter Control Register (RCM_RPFC)
317
Reset Pin Filter Width Register (RCM_RPFW)
318
Mode Register (RCM_MR)
319
Sticky System Reset Status Register 0 (RCM_SSRS0)
320
Sticky System Reset Status Register 1 (RCM_SSRS1)
321
System Mode Controller (SMC)
323
Introduction
323
Modes of Operation
323
Memory Map and Register Descriptions
325
Power Mode Protection Register (SMC_PMPROT)
326
Power Mode Control Register (SMC_PMCTRL)
327
Stop Control Register (SMC_STOPCTRL)
329
Power Mode Status Register (SMC_PMSTAT)
330
Functional Description
331
Power Mode Transitions
331
Power Mode Entry/Exit Sequencing
334
Run Modes
336
Wait Modes
338
Stop Modes
339
Debug in Low Power Modes
342
Power Management Controller (PMC)
345
Introduction
345
Features
345
Low-Voltage Detect (LVD) System
345
LVD Reset Operation
346
LVD Interrupt Operation
346
Low-Voltage Warning (LVW) Interrupt Operation
346
I/O Retention
347
Memory Map and Register Descriptions
347
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
348
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
349
Regulator Status and Control Register (PMC_REGSC)
350
Low-Leakage Wakeup Unit (LLWU)
353
Introduction
353
Features
353
Modes of Operation
354
Block Diagram
355
LLWU Signal Descriptions
356
Memory Map/Register Definition
356
LLWU Pin Enable 1 Register (LLWU_PE1)
357
LLWU Pin Enable 2 Register (LLWU_PE2)
358
LLWU Pin Enable 3 Register (LLWU_PE3)
359
LLWU Pin Enable 4 Register (LLWU_PE4)
360
LLWU Module Enable Register (LLWU_ME)
361
LLWU Flag 1 Register (LLWU_F1)
363
LLWU Flag 2 Register (LLWU_F2)
365
LLWU Flag 3 Register (LLWU_F3)
366
LLWU Pin Filter 1 Register (LLWU_FILT1)
368
LLWU Pin Filter 2 Register (LLWU_FILT2)
369
Functional Description
370
LLS Mode
371
VLLS Modes
371
Initialization
371
Miscellaneous Control Module (MCM)
373
Introduction
373
Features
373
Memory Map/Register Descriptions
373
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
374
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
374
Crossbar Switch (AXBS) Control Register (MCM_PLACR)
375
Interrupt Status and Control Register (MCM_ISCR)
376
Compute Operation Control Register (MCM_CPO)
379
Functional Description
380
Interrupts
380
Crossbar Switch Lite (AXBS-Lite)
381
Introduction
381
Features
381
Memory Map / Register Definition
382
Functional Description
382
General Operation
382
Arbitration
383
Initialization/Application Information
384
Peripheral Bridge (AIPS-Lite)
387
Introduction
387
Features
387
General Operation
387
Functional Description
388
Access Support
388
Direct Memory Access Multiplexer (DMAMUX)
389
Introduction
389
Overview
389
Features
390
Modes of Operation
390
External Signal Description
391
Memory Map/Register Definition
391
Channel Configuration Register (Dmamux_Chcfgn)
392
Functional Description
393
DMA Channels with Periodic Triggering Capability
393
DMA Channels with no Triggering Capability
395
Always-Enabled DMA Sources
396
Initialization/Application Information
397
Reset
397
Enabling and Configuring Sources
397
Enhanced Direct Memory Access (Edma)
401
Introduction
401
Edma System Block Diagram
401
Block Parts
402
Features
404
Modes of Operation
405
Memory Map/Register Definition
405
TCD Memory
405
TCD Initialization
406
TCD Structure
407
Reserved Memory and Bit Fields
408
Control Register (DMA_CR)
418
Error Status Register (DMA_ES)
421
Enable Request Register (DMA_ERQ)
423
Enable Error Interrupt Register (DMA_EEI)
425
Clear Enable Error Interrupt Register (DMA_CEEI)
427
Set Enable Error Interrupt Register (DMA_SEEI)
428
Clear Enable Request Register (DMA_CERQ)
429
Set Enable Request Register (DMA_SERQ)
430
Clear DONE Status Bit Register (DMA_CDNE)
431
Set START Bit Register (DMA_SSRT)
432
Clear Error Register (DMA_CERR)
433
Clear Interrupt Request Register (DMA_CINT)
434
Interrupt Request Register (DMA_INT)
435
Error Register (DMA_ERR)
437
Hardware Request Status Register (DMA_HRS)
440
Enable Asynchronous Request in Stop Register (DMA_EARS)
443
Channel N Priority Register (Dma_Dchprin)
445
TCD Source Address (Dma_Tcdn_Saddr)
446
TCD Signed Source Address Offset (Dma_Tcdn_Soff)
446
TCD Transfer Attributes (Dma_Tcdn_Attr)
447
TCD Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
448
(Dma_Tcdn_Nbytes_Mloffno)
449
(Dma_Tcdn_Nbytes_Mloffyes)
450
TCD Last Source Address Adjustment (Dma_Tcdn_Slast)
451
TCD Destination Address (Dma_Tcdn_Daddr)
452
TCD Signed Destination Address Offset (Dma_Tcdn_Doff)
452
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
453
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
454
TCD Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
455
TCD Control and Status (Dma_Tcdn_Csr)
456
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
458
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
459
Functional Description
460
Edma Basic Data Flow
460
Fault Reporting and Handling
463
Channel Preemption
465
Performance
465
Initialization/Application Information
470
Edma Initialization
470
Programming Errors
472
Arbitration Mode Considerations
472
Performing DMA Transfers
473
Monitoring Transfer Descriptor Status
477
Channel Linking
479
Dynamic Programming
480
External Watchdog Monitor (EWM)
485
Introduction
485
Features
485
Modes of Operation
486
Block Diagram
487
EWM Signal Descriptions
488
Memory Map/Register Definition
488
Control Register (EWM_CTRL)
488
Service Register (EWM_SERV)
489
Compare Low Register (EWM_CMPL)
489
Compare High Register (EWM_CMPH)
490
Clock Prescaler Register (EWM_CLKPRESCALER)
491
Functional Description
491
The Ewm_Out Signal
491
The Ewm_In Signal
492
EWM Counter
493
EWM Compare Registers
493
EWM Refresh Mechanism
493
EWM Interrupt
494
Counter Clock Prescaler
494
Watchdog Timer (WDOG)
495
Introduction
495
Features
495
Functional Overview
497
Unlocking and Updating the Watchdog
498
Watchdog Configuration Time (WCT)
499
Refreshing the Watchdog
500
Windowed Mode of Operation
500
Watchdog Disabled Mode of Operation
500
Debug Modes of Operation
501
Testing the Watchdog
501
Quick Test
502
Byte Test
502
Backup Reset Generator
503
Generated Resets and Interrupts
504
Memory Map and Register Definition
504
Watchdog Status and Control Register High (WDOG_STCTRLH)
505
Watchdog Status and Control Register Low (WDOG_STCTRLL)
507
Watchdog Time-Out Value Register High (WDOG_TOVALH)
507
Watchdog Time-Out Value Register Low (WDOG_TOVALL)
508
Watchdog Window Register High (WDOG_WINH)
508
Watchdog Window Register Low (WDOG_WINL)
509
Watchdog Refresh Register (WDOG_REFRESH)
509
Watchdog Unlock Register (WDOG_UNLOCK)
509
Watchdog Timer Output Register High (WDOG_TMROUTH)
510
Watchdog Timer Output Register Low (WDOG_TMROUTL)
510
Watchdog Reset Count Register (WDOG_RSTCNT)
511
Watchdog Prescaler Register (WDOG_PRESC)
511
Watchdog Operation with 8-Bit Access
511
General Guideline
511
Refresh and Unlock Operations with 8-Bit Access
512
Restrictions on Watchdog Operation
513
Multipurpose Clock Generator (MCG)
515
Introduction
515
Features
515
Modes of Operation
519
External Signal Description
519
Memory Map/Register Definition
519
MCG Control 1 Register (MCG_C1)
520
MCG Control 2 Register (MCG_C2)
521
MCG Control 3 Register (MCG_C3)
522
MCG Control 4 Register (MCG_C4)
523
MCG Control 5 Register (MCG_C5)
524
MCG Control 6 Register (MCG_C6)
525
MCG Status Register (MCG_S)
527
MCG Status and Control Register (MCG_SC)
528
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
530
MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
530
MCG Control 7 Register (MCG_C7)
530
MCG Control 8 Register (MCG_C8)
531
Functional Description
532
MCG Mode State Diagram
532
Low-Power Bit Usage
537
MCG Internal Reference Clocks
537
External Reference Clock
538
MCG Fixed Frequency Clock
538
MCG PLL Clock
539
MCG Auto TRIM (ATM)
539
Initialization / Application Information
540
MCG Module Initialization Sequence
540
Using a 32.768 Khz Reference
543
MCG Mode Switching
543
Oscillator (OSC)
553
Introduction
553
Features and Modes
553
Block Diagram
554
OSC Signal Descriptions
554
External Crystal / Resonator Connections
555
External Clock Connections
556
Memory Map/Register Definitions
557
OSC Memory Map/Register Definition
557
Functional Description
559
OSC Module States
559
OSC Module Modes
561
Counter
563
Reference Clock Pin Requirements
563
Reset
563
Low Power Modes Operation
564
Interrupts
564
Flash Memory Controller (FMC)
565
Introduction
565
Overview
565
Features
566
Modes of Operation
566
External Signal Description
566
Memory Map and Register Descriptions
566
Flash Access Protection Register (FMC_PFAPR)
571
Flash Bank 0 Control Register (FMC_PFB0CR)
575
Flash Bank 1 Control Register (FMC_PFB1CR)
578
Cache Tag Storage (Fmc_Tagvdw0Sn)
580
Cache Tag Storage (Fmc_Tagvdw1Sn)
581
Cache Tag Storage (Fmc_Tagvdw2Sn)
582
Cache Tag Storage (Fmc_Tagvdw3Sn)
583
Cache Data Storage (Upper Word) (Fmc_Dataw0Snu)
583
Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
584
Cache Data Storage (Upper Word) (Fmc_Dataw1Snu)
584
Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
585
Cache Data Storage (Upper Word) (Fmc_Dataw2Snu)
585
Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
586
Cache Data Storage (Upper Word) (Fmc_Dataw3Snu)
586
Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
587
Functional Description
587
Default Configuration
587
Configuration Options
588
Speculative Reads
589
Initialization and Application Information
589
Flash Memory Module (FTFA)
591
Introduction
591
Features
592
Block Diagram
592
Glossary
593
External Signal Description
594
Memory Map and Registers
595
Flash Configuration Field Description
595
Program Flash IFR Map
595
Register Descriptions
596
Functional Description
610
Flash Protection
610
Flash Access Protection
611
Interrupts
612
Flash Operation in Low-Power Modes
613
Functional Modes of Operation
613
Flash Reads and Ignored Writes
613
Read While Write (RWW)
614
Flash Program and Erase
614
Flash Command Operations
614
Margin Read Commands
619
Flash Command Description
621
Security
636
Reset Sequence
638
Overview
641
Block Diagram
642
Features
642
Modes of Operation
642
External Signal Descriptions
643
Ezport Clock (EZP_CK)
643
Ezport Chip Select (EZP_CS)
644
Ezport Serial Data in (EZP_D)
644
Ezport Serial Data out (EZP_Q)
644
Command Definition
644
Command Descriptions
645
Flash Memory Map for Ezport Access
652
External Bus Interface (Flexbus)
655
Introduction
655
Definition
655
Features
656
Signal Descriptions
656
Memory Map/Register Definition
659
Chip Select Address Register (Fb_Csarn)
660
Chip Select Mask Register (Fb_Csmrn)
661
Chip Select Control Register (Fb_Cscrn)
662
Chip Select Port Multiplexing Control Register (FB_CSPMCR)
665
Functional Description
666
Modes of Operation
666
Address Comparison
667
Address Driven on Address Bus
667
Connecting Address/Data Lines
667
Bit Ordering
667
Data Transfer Signals
668
Signal Transitions
668
Data-Byte Alignment and Physical Connections
668
Address/Data Bus Multiplexing
670
Data Transfer States
671
Flexbus Timing Examples
671
Burst Cycles
690
Extended Transfer Start/Address Latch Enable
698
Bus Errors
699
Initialization/Application Information
700
Initializing a Chip-Select
700
Reconfiguring a Chip-Select
700
Cyclic Redundancy Check (CRC)
701
Introduction
701
Features
701
Block Diagram
701
Modes of Operation
702
Memory Map and Register Descriptions
702
CRC Data Register (CRC_DATA)
703
CRC Polynomial Register (CRC_GPOLY)
704
CRC Control Register (CRC_CTRL)
704
Functional Description
705
CRC Initialization/Reinitialization
705
CRC Calculations
706
Transpose Feature
707
CRC Result Complement
709
Random Number Generator Accelerator (RNGA)
711
Introduction
711
Overview
711
Modes of Operation
712
Entering Normal Mode
712
Entering Sleep Mode
712
Memory Map and Register Definition
713
RNGA Control Register (RNG_CR)
713
RNGA Status Register (RNG_SR)
715
RNGA Entropy Register (RNG_ER)
717
RNGA Output Register (RNG_OR)
717
Functional Description
718
Output (OR) Register
718
Core Engine / Control Logic
718
Initialization/Application Information
719
Analog-To-Digital Converter (ADC)
721
Introduction
721
Features
721
Block Diagram
722
ADC Signal Descriptions
723
Analog Power (VDDA)
724
Analog Ground (VSSA)
724
Voltage Reference Select
724
Analog Channel Inputs (Adx)
725
Differential Analog Channel Inputs (Dadx)
725
Memory Map and Register Definitions
725
ADC Status and Control Registers 1 (Adcx_Sc1N)
727
ADC Configuration Register 1 (Adcx_Cfg1)
730
ADC Configuration Register 2 (Adcx_Cfg2)
732
ADC Data Result Register (Adcx_Rn)
733
Compare Value Registers (Adcx_Cvn)
734
Status and Control Register 2 (Adcx_Sc2)
735
Status and Control Register 3 (Adcx_Sc3)
737
ADC Offset Correction Register (Adcx_Ofs)
739
ADC Plus-Side Gain Register (Adcx_Pg)
739
ADC Minus-Side Gain Register (Adcx_Mg)
740
ADC Plus-Side General Calibration Value Register (Adcx_Clpd)
740
ADC Plus-Side General Calibration Value Register (Adcx_Clps)
741
ADC Plus-Side General Calibration Value Register (Adcx_Clp4)
741
ADC Plus-Side General Calibration Value Register (Adcx_Clp3)
742
ADC Plus-Side General Calibration Value Register (Adcx_Clp2)
742
ADC Plus-Side General Calibration Value Register (Adcx_Clp1)
743
ADC Plus-Side General Calibration Value Register (Adcx_Clp0)
743
ADC Minus-Side General Calibration Value Register (Adcx_Clmd)
744
ADC Minus-Side General Calibration Value Register (Adcx_Clms)
744
ADC Minus-Side General Calibration Value Register (Adcx_Clm4)
745
ADC Minus-Side General Calibration Value Register (Adcx_Clm3)
745
ADC Minus-Side General Calibration Value Register (Adcx_Clm2)
746
ADC Minus-Side General Calibration Value Register (Adcx_Clm1)
746
ADC Minus-Side General Calibration Value Register (Adcx_Clm0)
747
Functional Description
747
Clock Select and Divide Control
748
Voltage Reference Selection
749
Hardware Trigger and Channel Selects
749
Conversion Control
750
Automatic Compare Function
758
Calibration Function
759
User-Defined Offset Function
761
Temperature Sensor
762
MCU Wait Mode Operation
763
MCU Normal Stop Mode Operation
763
MCU Low-Power Stop Mode Operation
764
Initialization Information
765
ADC Module Initialization Example
765
Application Information
767
External Pins and Routing
767
Sources of Error
769
Comparator (CMP)
775
Introduction
775
CMP Features
775
6-Bit DAC Key Features
776
ANMUX Key Features
776
CMP, DAC and ANMUX Diagram
777
CMP Block Diagram
778
Memory Map/Register Definitions
780
CMP Control Register 0 (Cmpx_Cr0)
780
CMP Control Register 1 (Cmpx_Cr1)
781
CMP Filter Period Register (Cmpx_Fpr)
783
CMP Status and Control Register (Cmpx_Scr)
783
DAC Control Register (Cmpx_Daccr)
784
MUX Control Register (Cmpx_Muxcr)
785
Functional Description
786
CMP Functional Modes
786
Power Modes
795
Startup and Operation
796
Low-Pass Filter
797
CMP Interrupts
799
DMA Support
799
CMP Asynchronous DMA Support
800
Digital-To-Analog Converter
801
DAC Functional Description
801
Voltage Reference Source Select
801
DAC Resets
802
DAC Clocks
802
DAC Interrupts
802
12-Bit Digital-To-Analog Converter (DAC)
803
Introduction
803
Features
803
Block Diagram
803
Memory Map/Register Definition
804
DAC Data Low Register (Dacx_Datnl)
807
DAC Data High Register (Dacx_Datnh)
807
DAC Status Register (Dacx_Sr)
808
DAC Control Register (Dacx_C0)
809
DAC Control Register 1 (Dacx_C1)
810
DAC Control Register 2 (Dacx_C2)
811
Functional Description
811
DAC Data Buffer Operation
811
DMA Operation
813
Resets
813
Low-Power Mode Operation
813
Introduction
815
Overview
816
Features
816
Voltage Reference (VREFV1)
817
Modes of Operation
817
VREF Signal Descriptions
817
Memory Map and Register Definition
818
VREF Trim Register (VREF_TRM)
818
VREF Status and Control Register (VREF_SC)
819
Functional Description
820
Voltage Reference Disabled, SC[VREFEN] = 0
821
Voltage Reference Enabled, SC[VREFEN] = 1
821
Internal Voltage Regulator
822
Initialization/Application Information
823
Introduction
825
Features
825
Implementation
826
Programmable Delay Block (PDB)
827
Back-To-Back Acknowledgment Connections
827
DAC External Trigger Input Connections
827
Block Diagram
827
Modes of Operation
829
PDB Signal Descriptions
829
Memory Map and Register Definition
829
Status and Control Register (Pdbx_Sc)
831
Modulus Register (Pdbx_Mod)
833
Counter Register (Pdbx_Cnt)
834
Interrupt Delay Register (Pdbx_Idly)
834
Channel N Control Register 1 (Pdbx_Chnc1)
835
Channel N Status Register (Pdbx_Chns)
836
Channel N Delay 0 Register (Pdbx_Chndly0)
836
Channel N Delay 1 Register (Pdbx_Chndly1)
837
DAC Interval Trigger N Control Register (Pdbx_Dacintcn)
837
DAC Interval N Register (Pdbx_Dacintn)
838
Pulse-Out N Enable Register (Pdbx_Poen)
838
Pulse-Out N Delay Register (Pdbx_Pondly)
839
Functional Description
839
PDB Pre-Trigger and Trigger Outputs
839
PDB Trigger Input Source Selection
841
Pulse-Out's
841
Updating the Delay Registers
842
Interrupts
843
Dma
843
Application Information
844
Impact of Using the Prescaler and Multiplication Factor on Timing Resolution
844
Flextimer Module (FTM)
845
Introduction
845
Flextimer Philosophy
845
Features
846
Modes of Operation
847
Block Diagram
848
FTM Signal Descriptions
850
Memory Map and Register Definition
850
Memory Map
850
Register Descriptions
851
Status and Control (Ftmx_Sc)
857
Counter (Ftmx_Cnt)
858
Modulo (Ftmx_Mod)
859
Channel (N) Status and Control (Ftmx_Cnsc)
860
Channel (N) Value (Ftmx_Cnv)
863
Counter Initial Value (Ftmx_Cntin)
863
Capture and Compare Status (Ftmx_Status)
864
Features Mode Selection (Ftmx_Mode)
866
Synchronization (Ftmx_Sync)
868
Initial State for Channels Output (Ftmx_Outinit)
870
Output Mask (Ftmx_Outmask)
871
Function for Linked Channels (Ftmx_Combine)
873
Deadtime Insertion Control (Ftmx_Deadtime)
878
FTM External Trigger (Ftmx_Exttrig)
879
Channels Polarity (Ftmx_Pol)
881
Fault Mode Status (Ftmx_Fms)
883
Input Capture Filter Control (Ftmx_Filter)
885
Fault Control (Ftmx_Fltctrl)
886
Quadrature Decoder Control and Status (Ftmx_Qdctrl)
889
Configuration (Ftmx_Conf)
891
FTM Fault Input Polarity (Ftmx_Fltpol)
892
Synchronization Configuration (Ftmx_Synconf)
893
FTM Inverting Control (Ftmx_Invctrl)
895
FTM Software Output Control (Ftmx_Swoctrl)
896
FTM PWM Load (Ftmx_Pwmload)
899
Functional Description
900
Clock Source
901
Prescaler
902
Counter
902
Input Capture Mode
908
Output Compare Mode
911
Edge-Aligned PWM (EPWM) Mode
912
Center-Aligned PWM (CPWM) Mode
914
Combine Mode
916
Complementary Mode
923
Registers Updated from Write Buffers
924
PWM Synchronization
926
Inverting
942
Software Output Control
943
Deadtime Insertion
945
Output Mask
948
Fault Control
949
Polarity Control
952
Initialization
953
Features Priority
953
Channel Trigger Output
954
Initialization Trigger
955
Capture Test Mode
957
Dma
958
Dual Edge Capture Mode
959
Quadrature Decoder Mode
966
BDM Mode
971
Intermediate Load
972
Global Time Base (GTB)
974
Reset Overview
976
FTM Interrupts
977
Timer Overflow Interrupt
978
Channel (N) Interrupt
978
Fault Interrupt
978
Initialization Procedure
978
Periodic Interrupt Timer (PIT)
981
Introduction
981
Block Diagram
981
Features
982
Signal Description
982
Memory Map/Register Description
983
PIT Module Control Register (PIT_MCR)
983
Timer Load Value Register (Pit_Ldvaln)
985
Current Timer Value Register (Pit_Cvaln)
985
Timer Control Register (Pit_Tctrln)
986
Timer Flag Register (Pit_Tflgn)
986
Functional Description
987
General Operation
987
Interrupts
989
Chained Timers
989
Initialization and Application Information
989
Example Configuration for Chained Timers
990
Low-Power Timer (LPTMR)
993
Modes of Operation
993
LPTMR Signal Descriptions
994
Detailed Signal Descriptions
994
Memory Map and Register Definition
994
Low Power Timer Control Status Register (Lptmrx_Csr)
995
Low Power Timer Prescale Register (Lptmrx_Psr)
996
Low Power Timer Compare Register (Lptmrx_Cmr)
998
Low Power Timer Counter Register (Lptmrx_Cnr)
998
Functional Description
999
LPTMR Power and Reset
999
LPTMR Clocking
999
LPTMR Prescaler/Glitch Filter
999
LPTMR Compare
1001
LPTMR Counter
1001
LPTMR Hardware Trigger
1002
LPTMR Interrupt
1002
Serial Peripheral Interface (SPI)
1003
Introduction
1003
Block Diagram
1003
Features
1004
Interface Configurations
1006
Modes of Operation
1006
Module Signal Descriptions
1008
PCS0/SS-Peripheral Chip Select/Slave Select
1008
PCS1-PCS3-Peripheral Chip Selects 1-3
1009
PCS4-Peripheral Chip Select 4
1009
PCS5/PCSS-Peripheral Chip Select 5/Peripheral Chip Select Strobe
1009
SCK-Serial Clock
1009
SIN-Serial Input
1009
SOUT-Serial Output
1010
Memory Map/Register Definition
1010
Module Configuration Register (Spix_Mcr)
1012
Transfer Count Register (Spix_Tcr)
1015
Clock and Transfer Attributes Register (in Master Mode) (Spix_Ctarn)
1015
Clock and Transfer Attributes Register (in Slave Mode) (Spix_Ctarn_Slave)
1020
Status Register (Spix_Sr)
1022
Dma/Interrupt Request Select and Enable Register (Spix_Rser)
1025
PUSH TX FIFO Register in Master Mode (Spix_Pushr)
1027
PUSH TX FIFO Register in Slave Mode (Spix_Pushr_Slave)
1028
POP RX FIFO Register (Spix_Popr)
1029
Transmit FIFO Registers (Spix_Txfrn)
1030
Receive FIFO Registers (Spix_Rxfrn)
1030
Functional Description
1031
Start and Stop of Module Transfers
1032
Serial Peripheral Interface (SPI) Configuration
1032
Module Baud Rate and Clock Delay Generation
1036
Transfer Formats
1040
Continuous Serial Communications Clock
1045
Slave Mode Operation Constraints
1046
Interrupts/Dma Requests
1047
Power Saving Features
1049
Initialization/Application Information
1050
How to Manage Queues
1050
Switching Master and Slave Mode
1051
Initializing Module in Master/Slave Modes
1051
Baud Rate Settings
1052
Delay Settings
1053
Calculation of FIFO Pointer Addresses
1053
Introduction
1057
Features
1057
Modes of Operation
1058
Block Diagram
1058
I2C Signal Descriptions
1059
Memory Map/Register Definition
1060
I2C Address Register 1 (I2Cx_A1)
1061
I2C Frequency Divider Register (I2Cx_F)
1061
I2C Control Register 1 (I2Cx_C1)
1062
I2C Status Register (I2Cx_S)
1064
I2C Data I/O Register (I2Cx_D)
1066
I2C Control Register 2 (I2Cx_C2)
1066
I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
1067
I2C Range Address Register (I2Cx_Ra)
1069
I2C Smbus Control and Status Register (I2Cx_Smb)
1069
I2C Address Register 2 (I2Cx_A2)
1071
I2C SCL Low Timeout Register High (I2Cx_Slth)
1071
I2C SCL Low Timeout Register Low (I2Cx_Sltl)
1072
Functional Description
1072
I2C Protocol
1072
10-Bit Address
1077
Address Matching
1079
System Management Bus Specification
1080
Resets
1082
Interrupts
1082
Programmable Input Glitch Filter
1085
Address Matching Wake-Up
1085
DMA Support
1086
Initialization/Application Information
1087
Introduction
1091
Features
1091
Modes of Operation
1093
UART Signal Descriptions
1094
Detailed Signal Descriptions
1094
Memory Map and Registers
1095
UART Baud Rate Registers: High (Uartx_Bdh)
1100
UART Baud Rate Registers: Low (Uartx_Bdl)
1101
UART Control Register 1 (Uartx_C1)
1102
UART Control Register 2 (Uartx_C2)
1103
UART Status Register 1 (Uartx_S1)
1105
UART Status Register 2 (Uartx_S2)
1108
UART Control Register 3 (Uartx_C3)
1110
UART Data Register (Uartx_D)
1111
UART Match Address Registers 1 (Uartx_Ma1)
1112
UART Match Address Registers 2 (Uartx_Ma2)
1113
UART Control Register 4 (Uartx_C4)
1113
UART Control Register 5 (Uartx_C5)
1114
UART Extended Data Register (Uartx_Ed)
1115
UART Modem Register (Uartx_Modem)
1116
UART Infrared Register (Uartx_Ir)
1117
UART FIFO Parameters (Uartx_Pfifo)
1118
UART FIFO Control Register (Uartx_Cfifo)
1119
UART FIFO Status Register (Uartx_Sfifo)
1120
UART FIFO Transmit Watermark (Uartx_Twfifo)
1121
UART FIFO Transmit Count (Uartx_Tcfifo)
1122
UART FIFO Receive Watermark (Uartx_Rwfifo)
1122
UART FIFO Receive Count (Uartx_Rcfifo)
1123
UART 7816 Control Register (Uartx_C7816)
1123
UART 7816 Interrupt Enable Register (Uartx_Ie7816)
1125
UART 7816 Interrupt Status Register (Uartx_Is7816)
1126
UART 7816 Wait Parameter Register (Uartx_Wp7816)
1128
UART 7816 Wait N Register (Uartx_Wn7816)
1128
UART 7816 Wait FD Register (Uartx_Wf7816)
1129
UART 7816 Error Threshold Register (Uartx_Et7816)
1129
UART 7816 Transmit Length Register (Uartx_Tl7816)
1130
UART 7816 ATR Duration Timer Register a (Uartx_Ap7816A_T0)
1130
UART 7816 ATR Duration Timer Register B (Uartx_Ap7816B_T0)
1131
UART 7816 Wait Parameter Register a (Uartx_Wp7816A_T0)
1132
UART 7816 Wait Parameter Register a (Uartx_Wp7816A_T1)
1132
UART 7816 Wait Parameter Register B (Uartx_Wp7816B_T0)
1133
UART 7816 Wait Parameter Register B (Uartx_Wp7816B_T1)
1133
UART 7816 Wait and Guard Parameter Register (Uartx_Wgp7816_T1)
1134
UART 7816 Wait Parameter Register C (Uartx_Wp7816C_T1)
1134
Functional Description
1135
Transmitter
1135
Receiver
1141
Baud Rate Generation
1155
Data Format (Non ISO-7816)
1157
Single-Wire Operation
1160
Loop Operation
1161
ISO-7816/Smartcard Support
1161
Infrared Interface
1167
Reset
1168
System Level Interrupt Sources
1168
RXEDGIF Description
1168
DMA Operation
1169
Application Information
1170
Initialization Sequence
1170
Initialization Sequence (Non ISO-7816)
1172
Overrun (OR) Flag Implications
1173
Overrun NACK Considerations
1174
Match Address Registers
1175
Modem Feature
1175
Irda Minimum Pulse Width
1176
Clearing 7816 Wait Timer (WT, BWT, CWT) Interrupts
1176
Legacy and Reverse Compatibility Considerations
1177
Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
1179
Introduction
1179
Features
1179
Modes of Operation
1180
Signal Descriptions
1180
Block Diagram
1181
Register Definition
1182
LPUART Baud Rate Register (Lpuartx_Baud)
1183
LPUART Status Register (Lpuartx_Stat)
1185
LPUART Control Register (Lpuartx_Ctrl)
1189
LPUART Data Register (Lpuartx_Data)
1194
LPUART Match Address Register (Lpuartx_Match)
1196
LPUART Modem Irda Register (Lpuartx_Modir)
1196
Functional Description
1198
Baud Rate Generation
1198
Transmitter Functional Description
1199
Receiver Functional Description
1202
Additional LPUART Functions
1208
Infrared Interface
1210
Interrupts and Status Flags
1211
Introduction
1213
Features
1213
Modes of Operation
1213
General-Purpose Input/Output (GPIO)
1214
GPIO Signal Descriptions
1214
Memory Map and Register Definition
1215
Port Data Output Register (Gpiox_Pdor)
1217
Port Set Output Register (Gpiox_Psor)
1218
Port Clear Output Register (Gpiox_Pcor)
1218
Port Toggle Output Register (Gpiox_Ptor)
1219
Port Data Input Register (Gpiox_Pdir)
1219
Port Data Direction Register (Gpiox_Pddr)
1220
Functional Description
1220
General-Purpose Input
1220
General-Purpose Output
1220
JTAG Controller (JTAGC)
1223
Introduction
1223
Block Diagram
1223
Features
1224
Modes of Operation
1224
External Signal Description
1226
TCK-Test Clock Input
1226
TDI-Test Data Input
1226
TDO-Test Data Output
1226
TMS-Test Mode Select
1226
Register Description
1227
Instruction Register
1227
Bypass Register
1227
Device Identification Register
1227
Boundary Scan Register
1228
Functional Description
1229
JTAGC Reset Configuration
1229
IEEE 1149.1-2001 (JTAG) Test Access Port
1229
TAP Controller State Machine
1229
JTAGC Block Instructions
1231
Boundary Scan
1234
Initialization/Application Information
1234

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