Freescale Semiconductor HCS12 Reference Manual

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Page 1 S12CPUV2 Reference Manual HCS12 Microcontrollers S12CPUV2 Rev. 4.0 03/2006 freescale.com...
Page 3 Revision Date Summary of Changes Number April, 2002 Incorporated information covering HCS12 Family of 16-bit MCUs throughout the book. March, 2006 Reformatted to Freescale publication standards. Corrected mistake in ANDCC/TAP descriptions (Instruction Glossary). Corrected mistake in MEM description (Instruction Glossary).
Page 4 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 5: Table Of Contents
Index ..........433 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 6 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 7: Table Of Contents
Instruction Queue ......... . .28 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 8 4.2.2 HCS12 Queue Implementation.......48 Data Movement in the Queue ........48 4.3.1...
Page 9 Jump and Subroutine Instructions ......78 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 10 Unimplemented Opcode Trap....... . .317 Software Interrupt Instruction (SWI) ......318 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 11 HCS12 Timing Detail ........324...
Page 12 Notation Used in Instruction Set Summary ..... . .377 Hexadecimal to Decimal Conversion ......402 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 13 Data Types ..........425 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 14 C.10 Instruction Set Orthogonality........431 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 15: Section 1. Introduction
1.1 Introduction This manual describes the features and operation of the core (central processing unit, or CPU, and development support functions) used in all HCS12 microcontrollers. For reference, information is provided for the M68HC12. 1.2 Features The CPU12 is a high-speed, 16-bit processing unit that has a programming model identical to that of the industry standard M68HC11 central processor unit (CPU).
Page 16: Symbols And Notation
H — Half-carry status bit I — Maskable interrupt control bit N — Negative status bit Z — Zero status bit V — Two’s complement overflow status bit C — Carry/Borrow status bit S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 17: Memory And Addressing
— Program overlay page (bank) number for extended memory (>64 Kbytes). Page — Program overlay page — High-order byte — Low-order byte — Content of register or memory location — Hexadecimal value — Binary value S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 18: Operators
Example: (A) ⇒ M means the content of accumulator A is transferred to memory location M. ⇔ — Exchange Example: D ⇔ X means exchange the contents of D with those of X. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 19: Definitions
For example, A7 is bit 7 of accumulator A. A range of bit locations is referred to by mnemonic and the numbers that define the range. For example, DATA[15:8] form the high byte of the data bus. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 20 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 21: Section 2. Overview
• 16-bit program counter (PC) • 8-bit condition code register (CCR) 8-BIT ACCUMULATORS A AND B 16-BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 2-1. Programming Model S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 22: Accumulators
When a subroutine is called, the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack. Normally, a return-from-subroutine (RTS) or a return-from-call (RTC) instruction is executed at the end of a subroutine. The return instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 23: Program Counter
2.2.5 Condition Code Register The condition code register (CCR), named for its five status indicators, contains: • Five status indicators • Two interrupt masking bits • STOP instruction control bit S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 24: S Control Bit
If the CPU encounters a STOP instruction while the S bit is set, it is treated like a no-operation (NOP) instruction and continues to the next instruction. Reset sets the S bit. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 25: Mask Bit
The I bit enables and disables maskable interrupt sources. By default, the I bit is set to 1 during reset. An instruction must clear the I bit to enable maskable interrupts. While the I bit is set, maskable interrupts can become S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 26: N Status Bit
2.2.5.8 C Status Bit The C bit is set when a carry occurs during addition or a borrow occurs during subtraction. The C bit also acts as an error flag for multiply and divide S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 27: Data Types
The CPU12 has special instructions that support use of expanded memory. Eight-bit values can be stored at any odd or even byte address in available memory. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 28: Instruction Queue
CPU executes more than one instruction at the same time, while the CPU12 always finishes executing an instruction before beginning to execute another. Refer to Section 4. Instruction Queue for more information. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 29: Section 3. Addressing Modes
3.3 Effective Address Each addressing mode except inherent mode generates a 16-bit effective address which is used during the memory reference portion of the instruction. Effective address computations do not require extra execution cycles. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 30 16-bit constant offset from X, Y, SP, or PC (16-bit offset) (16-bit offset in two extension bytes) Indexed-Indirect Pointer to operand is found at... INST [D,xysp] [D,IDX] (D accumulator offset) X, Y, SP, or PC plus the value in D S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 31: Inherent Addressing Mode
8-bit value is supplied. In this case the assembler will generate the 16-bit value $0067 because the CPU expects a 16-bit value in the instruction stream. Example: BRSET FOO,#$03,THERE S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 32: Direct Addressing Mode
16-bit word of data is read from addresses $0020 and $0021. After execution of this instruction, the X index register will have the value from address $0020 in its high-order half and the value from address $0021 in its low-order half. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 33: Extended Addressing Mode
If all the bits in memory that correspond to a 1 in the mask are not in the specified state, execution continues with the instruction immediately following the branch instruction. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 34: Indexed Addressing Modes
2. Determine whether a value in an accumulator is used as an offset 3. Enable automatic pre- or post-increment or pre- or post-decrement 4. Specify size of increment or decrement 5. Specify use of 5-, 9-, or 16-bit signed offsets S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 35 In some variations of indexed addressing, the effective address specifies the location of a value that points to the memory location affected by the operation. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 36 A special group of instructions cause this calculated effective address to be loaded into an index register for further calculations: • Load stack pointer with effective address (LEAS) • Load X with effective address (LEAX) • Load Y with effective address (LEAY) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 37: 5-Bit Constant Offset Indexed Addressing
These instructions do not alter the index registers so they will still be $1000 and $2000, respectively, after the instructions. The first instruction will load A with the value from address $10FF and the second instruction will load B with the value from address $1FEC. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 38: 16-Bit Constant Offset Indexed Addressing
X to form the address $100A. Next, an address pointer ($2000) is fetched from memory at $100A. Then, the value stored in location $2000 is read and loaded into the A accumulator. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 39: Auto Pre/Post Decrement/Increment Indexed Addressing
M68HC11, 16-bit operations like push register X onto stack (PSHX) and pull register X from stack (PULX) require multiple instructions to decrement the SP by one, then store X, then decrement SP by one again. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 40: Accumulator Offset Indexed Addressing
B changed on each pass, the index register would have to be reloaded with the reference value on each loop pass. The use of LDAA B,X is more efficient in the CPU12. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 41: Accumulator D Indirect Indexed Addressing
The only combinations of addressing modes that are not allowed are those with an immediate mode destination (the operand of an immediate mode instruction is data, not an address). For indexed moves, the reference index register may be X, Y, SP, or PC. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 42 PC-relative addressing with move instructions. The original M68HC12 implemented the instruction queue slightly differently than the newer HCS12. In the older M68HC12 implementation, the CPU did not maintain a pointer to the start of the instruction after the current instruction (what the user thinks of as the PC value during execution).
Page 43: Bit Manipulation Instructions
C0. Check whether an assembler makes the correction before using PC-relative moves. On the newer HCS12, the instruction queue was implemented such that an internal pointer, to the start of the next instruction, is always available. On the HCS12, PC-relative move instructions work as expected without any offset adjustment.
Page 44: Addressing More Than 64 Kbytes
PPAGE. This value selects the page the called subroutine resides upon and can be considered part of the effective address. For all addressing mode variations except indexed indirect modes, the new page value is S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 45 The RTC instruction restores the saved program page value and the return address from the stack. This causes execution to resume at the next instruction after the original CALL instruction. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 46 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 47: Section 4. Instruction Queue
For example, an instruction composed of five bytes does two program fetches and one optional fetch. If the first byte of the five-byte instruction was even-aligned, the optional fetch is converted into a free S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 48: Original M68Hc12 Queue Implementation
2. In these cases, information is latched into the buffer until the queue can advance. 4.2.2 HCS12 Queue Implementation There are three 16-bit stages in the instruction queue. Instructions enter the queue at stage 1 and shift out of stage 3 as the CPU executes instructions and fetches new ones into stage 1.
Page 49: No Movement
These changes are categorized as resets, interrupts, subroutine calls, conditional branches, and jumps. Generally speaking, resets and interrupts are considered to be related to events outside the current program context that require special processing, while S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 50: Exceptions
BSR uses relative addressing mode to generate the effective address of the subroutine, while JSR can use various other addressing modes. Both instructions calculate a return address, stack the address, then perform three program word fetches to refill the queue. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 51: Branches
Branch instructions have two execution cases: • The branch condition is satisfied, and a change of flow takes place. • The branch condition is not satisfied, and no change of flow occurs. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 52: Short Branches
In the “taken” case, the effective address of the branch is calculated using the 16-bit relative offset contained in the second word of the instruction. This address is loaded into the program counter, then the CPU performs three program word fetches at the new address. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 53: Bit Condition Branches
All forms of JMP perform three program word fetches at the new address to refill the instruction queue. 1. In the original M68HC12, the implementation of these two cycles are both program word fetches. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 54 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 55: Section 5. Instruction Set Overview
These minor differences are transparent for most users. In the M68HC12 and HCS12 architecture, all memory and input/output (I/O) are mapped in a common 64-Kbyte address space (memory-mapped I/O). This allows the same set of instructions to be used to access memory, I/O, and control registers.
Page 56: Load And Store Instructions
Effective address ⇒ SP LEAS Load effective address into SP Effective address ⇒ X LEAX Load effective address into X Effective address ⇒ Y LEAY Load effective address into Y Continued on next page S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 57: Transfer And Exchange Instructions
16 bits, a zero-extend operation is performed on the 8-bit register as it is copied into the 16-bit register. Section 6. Instruction Glossary contains information concerning other transfers and exchanges between 8- and 16-bit registers. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 58: Move Instructions
Table 5-3. Move Instructions Mnemonic Function Operation ) ⇒ M MOVB Move byte (8-bit) (M : M + 1 ) ⇒ M : M + 1 MOVW Move word (16-bit) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 59: Addition And Subtraction Instructions
(A) – (M) ⇒ A SUBA Subtract memory from A (B) – (M) ⇒ B SUBB Subtract memory from B (D) – (M : M + 1) ⇒ D SUBD Subtract memory from D (A:B) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 60: Binary-Coded Decimal Instructions
(A) to be used with the DAA instruction. Thus additional steps would be needed to adjust the result to correct BCD form. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 61: Decrement And Increment Instructions
(A) + $01 ⇒ A INCA Increment A (B) + $01 ⇒ B INCB Increment B (SP) + $0001 ⇒ SP Increment SP (X) + $0001 ⇒ X Increment X (Y) + $0001 ⇒ Y Increment Y S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 62: Compare And Test Instructions
Compare Y to memory (16-bit) Test Instructions Test memory for zero or minus (M) – $00 TSTA Test A for zero or minus (A) – $00 TSTB Test B for zero or minus (B) – $00 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 63: Boolean Logic Instructions
Two’s complement memory $00 – (A) ⇒ A or (A) + 1 ⇒ A NEGA Two’s complement A $00 – (B) ⇒ B or (B) + 1 ⇒ B NEGB Two’s complement B S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 64: Multiplication And Division Instructions
Remainder ⇒ D (D) ÷ (X) ⇒ X IDIV 16 by 16 integer divide (unsigned) Remainder ⇒ D (D) ÷ (X) ⇒ X IDIVS 16 by 16 integer divide (signed) Remainder ⇒ D S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 65: Bit Test And Manipulation Instructions
(M) • (mm) ⇒ M BCLR Clear bits in memory (A) • (M) BITA Bit test A (B) • (M) BITB Bit test B (M) + (mm) ⇒ M BSET Set bits in memory S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 66: Shift And Rotate Instructions
Rotate left memory through carry ROLA Rotate left A through carry ROLB Rotate left B through carry Rotate right memory through carry RORA Rotate right A through carry RORB Rotate right B through carry S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 67: Fuzzy Logic Instructions
Because they require a number of cycles to execute, rule evaluation instructions can be interrupted. Once the interrupt has been serviced, instruction execution resumes at the point the interrupt occurred. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 68: Fuzzy Logic Weighted Average Instruction
X points to a 4-byte data structure that describes a trapezoidal membership function as base intercept points and slopes (P1, P2, S1, S2) Y points at fuzzy input (RAM location) Continued on next page S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 69 ∑ ⇒ Results are placed in correct registers for EDIV immediately after WAV Resumes execution Recover immediate results from stack WAVR of interrupted WAV rather than initializing them to 0. instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 70: Maximum And Minimum Instructions
MAX of two unsigned 8-bit values MAX ((A), (M)) ⇒ A MAXA result to accumulator MAX of two unsigned 8-bit values MAX ((A), (M)) ⇒ M MAXM result to memory S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 71: Multiply And Accumulate Instruction
Mnemonic Function Operation ) × (M Multiply and accumulate (signed) (X+1) (Y+1) EMACS 16 bit by 16 bit ⇒ 32 bit + (M ~ M + 3) ⇒ M ~ M + 3 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 72: Table Interpolation Instructions
(M) + [(B) × ((M + 1) – (M))] ⇒ A 8-bit table lookup and interpolate Initialize B, and index before TBL. (no indirect addressing <ea> points to the first 8-bit table entry (M) modes allowed) B is fractional part of lookup value. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 73: Branch Instructions
• Signed branches are taken when comparison or test of signed quantities results in a specific combination of condition code register bits. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 74: Short Branch Instructions
Z + (N ⊕ V) = 0 Branch if greater than R ≤ M Z + (N ⊕ V) = 1 Branch if less than or equal R < M N ⊕ V = 1 Branch if less than S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 75: Long Branch Instructions
Z + (N ⊕ V) = 0 LBGT Long branch if greater than Z + (N ⊕ V) = 1 LBLE Long branch if less than or equal N ⊕ V = 1 LBLT Long branch if less than S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 76: Bit Condition Branch Instructions
Table 5-19. Bit Condition Branch Instructions Mnemonic Function Equation or Operation (M) • (mm) = 0 BRCLR Branch if selected bits clear (M) • (mm) = 0 BRSET Branch if selected bits set S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 77: Loop Primitive Instructions
Test counter and branch if ≠ 0 If (counter) not = 0, then branch; TBNE (counter = A, B, D, X,Y, or SP) else continue to next instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 78: Jump And Subroutine Instructions
PPAGE value and the return address so that execution resumes with the next instruction after CALL. For software compatibility, CALL and RTC execute correctly on devices that do not have expanded addressing capability. Table 5-21 summarizes the jump and subroutine instructions. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 79: Interrupt Instructions
The CPU12 uses a variation of the software interrupt for unimplemented opcode trapping. There are opcodes in all 256 positions in the page 1 opcode map, but only 54 of the 256 positions on page 2 of the opcode map S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 80 SP – 2 ⇒ SP; X ⇒ M TRAP (SP) (SP+1) opcode interrupt SP – 2 ⇒ SP; B : A ⇒ M (SP) (SP+1) SP – 1 ⇒ SP; CCR ⇒ M (SP) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 81: Index Manipulation Instructions
(A, B, CCR, D, X, Y, or SP) Exchange register to register ⇔ (A, B, CCR, D, X, Y, or SP) (D) ⇔ (X) XGDX EXchange D with X (D) ⇔ (Y) XGDY EXchange D with Y S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 82: Stacking Instructions
) ⇒ A : B; (SP) + 2 ⇒ SP PULD Pull D (SP) (SP+1) ) ⇒ X; (SP) + 2 ⇒ SP PULX Pull X (SP) (SP+1) ) ⇒ Y; (SP) + 2 ⇒ SP PULY Pull Y (SP) (SP+1) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 83: Pointer And Index Calculation Instructions
= X, Y, SP, or PC r ± constant ⇒Y or Load result of indexed addressing mode (r) + (accumulator) ⇒ Y LEAY effective address calculation into y index register r = X, Y, SP, or PC S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 84: Condition Code Instructions
(SP) 1 ⇒ C Set C bit 1 ⇒ I Set I bit 1 ⇒ V Set V bit (A) ⇒ CCR Transfer A to CCR (CCR) ⇒ A Transfer CCR to A S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 85: Stop And Wait Instructions
SP – 2 ⇒ SP; X ⇒ M Wait for interrupt (SP) (SP+1) SP – 2 ⇒ SP; B : A ⇒ M (SP) (SP+1) SP – 1 ⇒ SP; CCR ⇒ M (SP) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 86: Background Mode And Null Operations
Table 5-28. Background Mode and Null Operation Instructions Mnemonic Function Operation If BDM enabled, enter BDM; BGND Enter background debug mode else resume normal processing Branch never Does not branch LBRN Long branch never Does not branch Null operation — S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 87: Section 6. Instruction Glossary
Reference Manual — S12CPUV2 Section 6. Instruction Glossary 6.1 Introduction This section is a comprehensive reference to the CPU12 instruction set. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 88: Glossary Information
Each entry contains symbolic and textual descriptions of operation, information concerning the effect of operation on status bits in the condition code register, and a table that describes assembler syntax, address mode variations, and cycle-by-cycle execution of the instruction. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 89: Condition Code Changes
⇑ — Status bit may be set or remain cleared, but is not cleared by operation. ? — Status bit may be changed by operation, but the final state is not defined. ! — Status bit used for a special purpose S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 90: Object Code Notation
— Signed relative offset $80 (–128) to $7F (+127) offset relative to the byte following the relative offset byte, or low-order byte of a 16-bit relative offset for long branches xb — Indexed addressing post-byte S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 91: Source Forms
Assemblers also vary in the way CPU registers are specified. Refer to assembler documentation for detailed information. Recommended register designators are a, A, b, B, ccr, CCR, d, D, x, X, y, Y, sp, SP, pc, and S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 92 64-Kbyte address space ($00xx). opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this value as an address in the 64-Kbyte address space. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 93 –128 to +127 locations from the next address after the last byte of object code for the current instruction. The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 94: Cycle-By-Cycle Execution
16-bit access cycles. There are cycle codes for each addressing mode variation of each instruction. Simply count code letters to determine the execution time of an instruction in a best-case system. An S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 95 8-bit value for the memory expansion page register of the CALL destination is fetched from an indirect memory location. These cycles are stretched only when controlled by a chip-select circuit that is programmed for slow memory. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 96 MCU is operating with an 8-bit external data bus and the program is stored externally. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 97 — Unstack 8-bit data. These cycles are stretched only when controlled by a chip-select circuit programmed for slow memory. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 98 — 8-bit conditional write. These cycles are either data write cycles or free cycles, depending on the data and flow of the REV or REVW instruction. These cycles are only stretched when controlled by a chip-select circuit programmed for slow memory. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 99: Glossary
First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address. 6.7 Glossary This subsection contains an entry for each assembler mnemonic, in alphabetic order. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 100 C: A7 • B7 + B7 • R7 + R7 • A7 Set if there was a carry from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 18 06 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 101 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 1A E5 translates to... LEAX B,X 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction. S12CPUV2 Reference Manual, Rev. 4.0...
Page 102 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 19 ED translates to... LEAY B,Y 1. Due to internal M68HC12CPU requirements, the program word fetch is performed twice to the same address during this instruction. S12CPUV2 Reference Manual, Rev. 4.0...
Page 103 C: A7 • M7 + M7 • R7 + R7 • A7 Set if there was a carry from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ADCA #opr8i 89 ii ADCA opr8a 99 dd ADCA opr16a B9 hh ll...
Page 104 C: X7 • M7 + M7 • R7 + R7 • X7 Set if there was a carry from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ADCB #opr8i C9 ii ADCB opr8a D9 dd ADCB opr16a F9 hh ll...
Page 105 C: A7 • M7 + M7 • R7 + R7 • A7 Set if there was a carry from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ADDA #opr8i 8B ii ADDA opr8a 9B dd ADDA opr16a BB hh ll...
Page 106 C: B7 • M7 + M7 • R7 + R7 • B7 Set if there was a carry from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ADDB #opr8i CB ii ADDB opr8a DB dd ADDB opr16a FB hh ll...
Page 107 C: D15 • M15 + M15 • R15 + R15 • D15 Set if there was a carry from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ADDD #opr16i C3 jj kk ADDD opr8a D3 dd ADDD opr16a F3 hh ll...
Page 108 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ANDA #opr8i 84 ii ANDA opr8a 94 dd ANDA opr16a B4 hh ll...
Page 109 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ANDB #opr8i C4 ii ANDB opr8a D4 dd ANDB opr16a F4 hh ll...
Page 110 Condition code bits are cleared if the corresponding bit was 0 before the operation or if the corresponding bit in the mask is 0. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ANDCC #opr8i 10 ii S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 111 (for values of N and C after the shift) C: M7 Set if the MSB of M was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASL opr16a 78 hh ll rPwO rOPw ASL oprx0_xysp 68 xb...
Page 112 (for values of N and C after the shift) C: A7 Set if the MSB of A was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASLA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 113 (for values of N and C after the shift) C: B7 Set if the MSB of B was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASLB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 114 (for values of N and C after the shift) C: D15 Set if the MSB of D was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASLD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 115 (for values of N and C after the shift) C: M0 Set if the LSB of M was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASR opr16a 77 hh ll rPwO rOPw ASR oprx0_xysp 67 xb...
Page 116 (for values of N and C after the shift) C: A0 Set if the LSB of A was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASRA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 117 (for values of N and C after the shift) C: B0 Set if the LSB of B was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ASRB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 118 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BCC rel8 24 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 119 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BCLR opr8a, msk8 4D dd mm rPwO rPOw BCLR opr16a, msk8 1D hh ll mm...
Page 120 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BCS rel8 25 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 121 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BEQ rel8 27 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 122 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BGE rel8 2C rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 123 Refer to Section 8. Instruction Queue for more information concerning BDM. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BGND VfPPP VfPPP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 124 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BGT rel8 2E rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 125 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BHI rel8 22 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 126 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BHS rel8 24 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 127 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BITA #opr8i 85 ii BITA opr8a 95 dd BITA opr16a B5 hh ll...
Page 128 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BITB #opr8i C5 ii BITB opr8a D5 dd BITB opr16a F5 hh ll...
Page 129 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BLE rel8 2F rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 130 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BLO rel8 25 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 131 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BLS rel8 23 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 132 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BLT rel8 2D rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 133 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BMI rel8 2B rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 134 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BNE rel8 26 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 135 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BPL rel8 2A rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 136 3.8 Relative Addressing Mode for details of branch execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BRA rel8 20 rr S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 137 – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BRCLR opr8a, msk8, rel8 4F dd mm rr rPPP rPPP BRCLR opr16a, msk8, rel8 1F hh ll mm rr rfPPP rfPPP BRCLR oprx0_xysp, msk8, rel8...
Page 138 3.8 Relative Addressing Mode for details of branch execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BRN rel8 21 rr S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 139 – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BRSET opr8a, msk8, rel8 4E dd mm rr rPPP rPPP BRSET opr16a, msk8, rel8 1E hh ll mm rr rfPPP rfPPP BRSET oprx0_xysp, msk8, rel8...
Page 140 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BSET opr8a, msk8 4C dd mm rPwO rPOw BSET opr16a, msk8 1C hh ll mm...
Page 141 CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BSR rel8 07 rr SPPP PPPS S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 142 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BVC rel8 28 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 143 – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 BVS rel8 29 rr PPP/P PPP/P 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Page 144 – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CALL opr16a, page 4A hh ll pg gnSsPPP gnfSsPPP CALL oprx0_xysp, page 4B xb pg gnSsPPP gnfSsPPP CALL oprx9,xysp, page IDX1 4B xb ff pg...
Page 145 C: A7 • B7 + B7 • R7 + R7 • A7 Set if there was a borrow from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 18 17 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 146 CLC can be used to set up the C bit prior to a shift or rotate instruction involving the C bit. CCR Details: – – – – – – – C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 10 FE translates to... ANDCC #$FE S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 147 CLI instruction. CCR Details: – – – – – – – 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 10 EF translates to... ANDCC #$EF S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 148 – N: 0; cleared Z: 1; set V: 0; cleared C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CLR opr16a 79 hh ll CLR oprx0_xysp 69 xb CLR oprx9,xysp IDX1 69 xb ff CLR oprx16,xysp...
Page 149 All bits in accumulator A are cleared to 0. CCR Details: – – – – N: 0; cleared Z: 1; set V: 0; cleared C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CLRA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 150 All bits in accumulator B are cleared to 0. CCR Details: – – – – N: 0; cleared Z: 1; set V: 0; cleared C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CLRB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 151 ANDCC instruction can be used to clear any combination of bits in the CCR in one operation. CCR Details: – – – – – – – V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 10 FD translates to... ANDCC #$FD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 152 C: A7 • M7 + M7 • R7 + R7 • A7 Set if there was a borrow from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CMPA #opr8i 81 ii CMPA opr8a 91 dd CMPA opr16a B1 hh ll...
Page 153 C: B7 • M7 + M7 • R7 + R7 • B7 Set if there was a borrow from the MSB of the result; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CMPB #opr8i C1 ii CMPB opr8a D1 dd CMPB opr16a F1 hh ll...
Page 154 Z: Set if result is $00; cleared otherwise V: 0; cleared C: 1; set (for M6800 compatibility) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 COM opr16a 71 hh ll rPwO rOPw COM oprx0_xysp 61 xb COM oprx9...
Page 155 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared C: 1; set (for M6800 compatibility) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 COMA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 156 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared C: 1; set (for M6800 compatibility) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 COMB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 157 Set if the absolute value of the content of memory is larger than the absolute value of the accumulator; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CPD #opr16i 8C jj kk CPD opr8a 9C dd CPD opr16a...
Page 158 Set if the absolute value of the content of memory is larger than the absolute value of the SP; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CPS #opr16i 8F jj kk CPS opr8a 9F dd CPS opr16a...
Page 159 Set if the absolute value of the content of memory is larger than the absolute value of the index register; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CPX #opr16i 8E jj kk CPX opr8a 9E dd CPX opr16a...
Page 160 Set if the absolute value of the content of memory is larger than the absolute value of the index register; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 CPY #opr16i 8D jj kk CPY opr8a 9D dd CPY opr16a...
Page 161 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: Undefined C: Represents BCD carry. See bit table Access Detail Address Source Form Object Code Mode HCS12 M68HC12 18 07 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 162 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 DBEQ abdxys, rel9 04 lb rr PPP/PPO 1. Encoding for is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (DBEQ –...
Page 163 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 DBNE abdxys, rel9 04 lb rr PPP/PPO 1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (DBEQ – 0) or not zero (DBNE –...
Page 164 V: Set if there was a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (M) was $80 before the operation. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 DEC opr16a 73 hh ll rPwO rOPw DEC oprx0_xysp 63 xb...
Page 165 V: Set if there was a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (A) was $80 before the operation. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 DECA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 166 V: Set if there was a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (B) was $80 before the operation. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 DECB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 167 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 1B 9F translates to... LEAS –1,SP 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction. S12CPUV2 Reference Manual, Rev. 4.0...
Page 168 Only the Z bit is set or cleared according to the result of this operation. CCR Details: ∆ – – – – – – – Z: Set if result is $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 169 Only the Z bit is set or cleared according to the result of this operation. CCR Details: ∆ – – – – – – – Z: Set if result is $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 170 V: Set if the result was > $FFFF; cleared otherwise Undefined after division by zero C: Set if divisor was $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EDIV ffffffffffO ffffffffffO S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 171 V: Set if the result was > $7FFF or < $8000; cleared otherwise Undefined after division by zero C: Set if divisor was $0000; cleared otherwise Indicates division by zero Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EDIVS 18 14 OffffffffffO OffffffffffO S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 172 Set if there was a carry from bit 15 of the result; cleared otherwise Indicates a carry from low word to high word of the result occurred Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMACS opr16a Special 18 12 hh ll ORROfffRRfWWP ORROfffRRfWWP 1.
Page 173 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = D – M : M + 1) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMAXD oprx0_xysp 18 1A xb ORPf ORfP EMAXD oprx9,xysp IDX1...
Page 174 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = D – M : M + 1) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMAXM oprx0_xysp 18 1E xb ORPW ORPW EMAXM oprx9,xysp IDX1...
Page 175 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = D – M : M + 1) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMIND oprx0_xysp 18 1B xb ORPf ORfP EMIND oprx9,xysp IDX1...
Page 176 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = D – M : M + 1) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMINM oprx0_xysp 18 1F xb ORPW ORPW EMINM oprx9,xysp IDX1...
Page 177 N: Set if the MSB of the result is set; cleared otherwise Z: Set if result is $00000000; cleared otherwise C: Set if bit 15 of the result is set; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMUL S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 178 C: Set if bit 15 of the result is set; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EMULS 18 13 OffO 1. EMULS has an extra free cycle if it is followed by another PAGE TWO instruction.
Page 179 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EORA #opr8i 88 ii EORA opr8a 98 dd EORA opr16a B8 hh ll...
Page 180 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EORB #opr8i C8 ii EORB opr8a D8 dd EORB opr16a F8 hh ll...
Page 181 C: Set if result can be rounded up; cleared otherwise 1. C-bit was undefined in original M68HC12 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ETBL oprx0_xysp 18 3F xb ORRffffffP ORRffffffP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 182 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 EXG abcdxys,abcdxys B7 eb 1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent the low-order destination digit (bit 3 is a don’t care). Values are in hexadecimal.
Page 183 C: X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0 Set if denominator was $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 FDIV 18 11 OffffffffffO OffffffffffO S12CPUV2 Reference Manual, Rev. 4.0...
Page 184 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 IBEQ abdxys, rel9 04 lb rr PPP/PPO 1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (IBEQ –...
Page 185 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 IBNE abdxys, rel9 04 lb rr PPP/PPO 1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (IBEQ –...
Page 186 C: X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0 Set if denominator was $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 IDIV 18 10 OffffffffffO OffffffffffO S12CPUV2 Reference Manual, Rev. 4.0...
Page 187 C: X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0 Set if denominator was $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 IDIVS 18 15 OffffffffffO OffffffffffO S12CPUV2 Reference Manual, Rev. 4.0...
Page 188 V: Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (M) was $7F before the operation. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 INC opr16a 72 hh ll rPwO rOPw INC oprx0_xysp 62 xb...
Page 189 V: Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (A) was $7F before the operation. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 INCA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 190 V: Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (B) was $7F before the operation. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 INCB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 191 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 1B 81 translates to... LEAS 1,SP 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction. S12CPUV2 Reference Manual, Rev. 4.0...
Page 192 INX operation affects only the Z status bit. CCR Details: ∆ – – – – – – – Z: Set if result is $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 193 INY operation affects only the Z status bit. CCR Details: ∆ – – – – – – – Z: Set if result is $0000; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 194 – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 JMP opr16a 06 hh ll JMP oprx0_xysp 05 xb JMP oprx9,xysp IDX1 05 xb ff JMP oprx16,xysp IDX2 05 xb ee ff fPPP...
Page 195 CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 JSR opr8a 17 dd SPPP PPPS JSR opr16a 16 hh ll SPPP PPPS JSR oprx0_xysp 15 xb PPPS PPPS JSR oprx9,xysp...
Page 196 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBCC rel16 18 24 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 197 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBCS rel16 18 25 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 198 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBEQ rel16 18 27 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 199 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBGE rel16 18 2C qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 200 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBGT rel16 18 2E qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 201 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBHI rel16 18 22 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 202 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBHS rel16 18 24 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 203 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBLE rel16 18 2F qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 204 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBLO rel16 18 25 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 205 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBLS rel16 18 23 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 206 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBLT rel16 18 2D qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 207 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBMI rel16 18 2B qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 208 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBNE rel16 18 26 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 209 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBPL rel16 18 2A qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 210 CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBRA rel16 18 20 qq rr OPPP OPPP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 211 CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBRN rel16 18 21 qq rr S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 212 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBVC rel16 18 28 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 213 – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LBVS rel16 18 29 qq rr OPPP/OPO OPPP/OPO 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Page 214 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LDAA #opr8i 86 ii LDAA opr8a 96 dd LDAA opr16a B6 hh ll...
Page 215 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LDAB #opr8i C6 ii LDAB opr8a D6 dd LDAB opr16a F6 hh ll...
Page 216 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LDD #opr16i CC jj kk LDD opr8a DC dd LDD opr16a FC hh ll...
Page 217 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LDS #opr16i CF jj kk LDS opr8a DF dd LDS opr16a FF hh ll...
Page 218 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LDX #opr16i CE jj kk LDX opr8a DE dd LDX opr16a FE hh ll...
Page 219 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LDY #opr16i CD jj kk LDY opr8a DD dd LDY opr16a FD hh ll...
Page 220 – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LEAS oprx0_xysp 1B xb LEAS oprx9,xysp IDX1 1B xb ff LEAS oprx16,xysp IDX2 1B xb ee ff 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction.
Page 221 – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LEAX oprx0_xysp 1A xb LEAX oprx9,xysp IDX1 1A xb ff LEAX oprx16,xysp IDX2 1A xb ee ff 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction.
Page 222 – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LEAY oprx0_xysp 19 xb LEAY oprx9,xysp IDX1 19 xb ff LEAY oprx16,xysp IDX2 19 xb ee ff 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction.
Page 223 (for values of N and C after the shift) C: M7 Set if the LSB of M was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSL opr16a 78 hh ll rPwO rOPw LSL oprx0_xysp 68 xb...
Page 224 (for values of N and C after the shift) C: A7 Set if the LSB of A was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSLA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 225 (for values of N and C after the shift) C: B7 Set if the LSB of B was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSLB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 226 (for values of N and C after the shift) C: D15 Set if the MSB of D was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSLD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 227 (for values of N and C after the shift) C: M0 Set if the LSB of M was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSR opr16a 74 hh ll rPwO rOPw LSR oprx0_xysp 64 xb...
Page 228 (for values of N and C after the shift) C: A0 Set if the LSB of A was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSRA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 229 (for values of N and C after the shift) C: B0 Set if the LSB of B was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSRB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 230 Set if, after the shift operation, C is set; cleared otherwise C: D0 Set if the LSB of D was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 LSRD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 231 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = A – M) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 MAXA oprx0_xysp 18 18 xb OrPf OrfP MAXA oprx9,xysp IDX1...
Page 232 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = A – M) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 MAXM oprx0_xysp 18 1C xb OrPw OrPw MAXM oprx9,xysp IDX1...
Page 233 Y is incremented by one. CCR Details: – – – H, N, Z, V, and C may be altered by this instruction. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 Special RRfOw RRfOw S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 234 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = A – M) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 MINA oprx0_xysp 18 19 xb OrPf OrfP MINA oprx9,xysp IDX1...
Page 235 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Condition codes reflect internal subtraction (R = A – M) Access Detail Address Source Form Object Code Mode HCS12 M68HC12 MINM oprx0_xysp 18 1D xb OrPw OrPw MINM oprx9,xysp IDX1...
Page 236 – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 MOVB #opr8, opr16a IMM–EXT 18 0B ii hh ll OPwP OPwP MOVB #opr8i, oprx0_xysp IMM–IDX 18 08 xb ii OPwO OPwO MOVB opr16a, opr16a EXT–EXT...
Page 237 – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 MOVW #opr16i, opr16a IMM–EXT 18 03 jj kk hh ll OPWPO OPWPO MOVW #opr16i, oprx0_xysp IMM–IDX 18 00 xb jj kk OPPW OPPW MOVW opr16a, opr16a EXT–EXT...
Page 238 – – – – – – – C: R7 Set if bit 7 of the result (B bit 7) is set; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 239 Set if there is a borrow in the implied subtraction from zero; cleared otherwise. Set in all cases except when (M) = $00. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 NEG opr16a 70 hh ll rPwO rOPw NEG oprx0_xysp...
Page 240 Set if there is a borrow in the implied subtraction from zero; cleared otherwise Set in all cases except when (A) = $00 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 NEGA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 241 Set if there is a borrow in the implied subtraction from zero; cleared otherwise Set in all cases except when (B) = $00 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 NEGB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 242 CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 243 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ORAA #opr8i 8A ii ORAA opr8a 9A dd ORAA opr16a BA hh ll...
Page 244 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ORAB #opr8i CA ii ORAB opr8a DA dd ORAB opr16a FA hh ll...
Page 245 1. The X interrupt mask cannot be set by any software instruction. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ORCC #opr8i 14 ii S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 246 CPU registers just before returning from the subroutine. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PSHA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 247 CPU registers just before returning from the subroutine. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PSHB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 248 CPU registers just before returning from the subroutine. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PSHC S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 249 CPU registers just before returning from the subroutine. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PSHD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 250 CPU registers just before returning from the subroutine. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PSHX S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 251 CPU registers just before returning from the subroutine. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PSHY S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 252 CPU registers that were pushed onto the stack before subroutine execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PULA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 253 CPU registers that were pushed onto the stack before subroutine execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PULB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 254 1 to 0, but it can be set only by a reset or by recognition of an XIRQ interrupt. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PULC S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 255 CPU registers that were pushed onto the stack before subroutine execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PULD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 256 CPU registers that were pushed onto the stack before subroutine execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PULX S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 257 CPU registers that were pushed onto the stack before subroutine execution. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 PULY S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 258 X is automatically updated so that execution can resume correctly if the instruction is interrupted. When execution is complete, X points to the next address after the $FF separator at the end of the rule list. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 259 V: 1; Normally set, unless rule structure is erroneous H, N, Z, and C may be altered by this instruction Access Detail Address Source Form Object Code Mode HCS12 M68HC12 Orf(t,tx)O Orf(t,tx)O Special 18 3A ff + Orf(t, (replace comma if interrupted) ff + Orf(t, 1.
Page 260 • Clear fuzzy outputs to 0s. • Set or clear the CCR C bit. When weighted evaluation is enabled, Y must point to the first item in a table of 8-bit weighting factors. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 261 Fuzzy outputs must be cleared to $00 before processing begins in order for the MAX algorithm used during consequent processing to work correctly. Residual output values would cause incorrect comparison. Refer to Section 9. Fuzzy Logic Support for details. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 262 C: Selects weighted (1) or unweighted (0) rule evaluation H, N, Z, and C may be altered by this instruction Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ORf(t,Tx)O REVW ORf(tTx)O (add 2 at end of ins if wts) Special...
Page 263 (for values of N and C after the shift) C: M7 Set if the MSB of M was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ROL opr16a 75 hh ll rPwO rOPw ROL oprx0_xysp 65 xb...
Page 264 (for values of N and C after the shift) C: A7 Set if the MSB of A was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ROLA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 265 (for values of N and C after the shift) C: B7 Set if the MSB of B was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ROLB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 266 (for values of N and C after the shift) C: M0 Set if the LSB of M was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 ROR opr16a 76 hh ll rPwO rOPw ROR oprx0_xysp 66 xb...
Page 267 (for values of N and C after the shift) C: A0 Set if the LSB of A was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 RORA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 268 (for values of N and C after the shift) C: B0 Set if the LSB of B was set before the shift; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 RORB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 269 CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 uUnfPPP uUnPPP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 270 1 to 0, but it can be set only by a reset or by recognition of an XIRQ interrupt. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 uUUUUPPP uUUUUPPP (with interrupt pending) uUUUUfVfPPP uUUUUVfPPP S12CPUV2 Reference Manual, Rev.
Page 271 16-bit value pulled from the stack and increments the stack pointer by two. Program execution continues at the address restored from the stack. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 UfPPP UfPPP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 272 C: A7 • B7 + B7 • R7 + R7 • A7 Set if the absolute value of B is larger than the absolute value of A; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 18 16 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 273 Set if the absolute value of the content of memory plus previous carry is larger than the absolute value of the accumulator; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 SBCA #opr8i 82 ii SBCA opr8a 92 dd SBCA opr16a B2 hh ll...
Page 274 Set if the absolute value of the content of memory plus previous carry is larger than the absolute value of the accumulator; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 SBCB #opr8i C2 ii SBCB opr8a D2 dd SBCB opr16a F2 hh ll...
Page 275 SEC can be used to set up the C bit prior to a shift or rotate instruction involving the C bit. CCR Details: – – – – – – – C: 1; set Access Detail Address Source Form Object Code Mode HCS12 M68HC12 14 01 translates to... ORCC #$01 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 276 CPU will recognize only non-maskable interrupt sources or an SWI. CCR Details: – – – – – – – 1; set Access Detail Address Source Form Object Code Mode HCS12 M68HC12 14 10 translates to... ORCC #$10 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 277 ORCC instruction can be used to set any combination of bits in the CCR in one operation. CCR Details: – – – – – – – V: 1; set Access Detail Address Source Form Object Code Mode HCS12 M68HC12 14 02 translates to... ORCC #$02 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 278 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 SEX abc,dxys B7 eb 1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent the low-order destination digit (MSB is a don’t care). Values are in hexadecimal.
Page 279 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STAA opr8a 5A dd STAA opr16a 7A hh ll STAA oprx0_xysp 6A xb...
Page 280 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STAB opr8a 5B dd STAB opr16a 7B hh ll STAB oprx0_xysp 6B xb...
Page 281 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STD opr8a 5C dd STD opr16a 7C hh ll STD oprx0_xysp 6C xb...
Page 282 – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STOP (entering STOP) 18 3E OOSSSSsf OOSSSfSs (exiting STOP) fVfPPP fVfPPP (continue) (if STOP disabled) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 283 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STS opr8a 5F dd STS opr16a 7F hh ll STS oprx0_xysp 6F xb...
Page 284 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STX opr8a 5E dd STX opr16a 7E hh ll STX oprx0_xysp 6E xb...
Page 285 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $0000; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 STY opr8a 5D dd STY opr16a 7D hh ll STY oprx0_xysp 6D xb...
Page 286 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 SUBA #opr8i 80 ii SUBA opr8a 90 dd SUBA opr16a B0 hh ll...
Page 287 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 SUBB #opr8i C0 ii SUBB opr8a D0 dd SUBB opr16a F0 hh ll...
Page 288 Set if the value of the content of memory is larger than the value of the accumulator; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 SUBD #opr16i 83 jj kk SUBD opr8a 93 dd SUBD opr16a...
Page 289: Section 7. Exception Processing
1; set Access Detail Address Source Form Object Code Mode HCS12 M68HC12 VSPSSPSsP VSPSSPSsP 1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A variation of the sequence (VfPPP) is used for resets.
Page 290 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 18 0E S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 291 X bit set, leave it cleared, or change it from 1 to 0, but it can only be set by a reset or by recognition of an XIRQ interrupt. Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TAP translates to... B7 02 TFR A,CCR S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 292 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 18 0F S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 293 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TBEQ abdxys,rel9 04 lb rr PPP/PPO 1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (TBEQ – 0) or not zero (TBNE –...
Page 294 Z: Set if result is $00; cleared otherwise C: Set if result can be rounded up; cleared otherwise Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TBL oprx0_xysp 18 3D xb ORfffP OrrffffP S12CPUV2 Reference Manual, Rev. 4.0...
Page 295 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TBNE abdxys,rel9 04 lb rr PPP/PPO 1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (TBEQ –...
Page 296 Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TFR abcdxys,abcdxys B7 eb 1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent the low-order destination digit (MSB is a don’t-care). Values are in hexadecimal.
Page 297 M68HC11, the mnemonic TPA is translated into the TFR CCR,A instruction by the assembler. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 B7 20 translates to... TFR CCR,A S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 298: Section 7. Exception Processing
1; set Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TRAP trapnum $18 tn OVSPSSPSsP OfVSPSSPSsP 1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF.
Page 299 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TST opr16a F7 hh ll TST oprx0_xysp E7 xb TST oprx9,xysp IDX1 E7 xb ff...
Page 300 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TSTA S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 301 N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: 0; cleared C: 0; cleared Access Detail Address Source Form Object Code Mode HCS12 M68HC12 TSTB S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 302 X points at the last value that was stored on the stack. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 B7 75 translates to... TFR SP,X S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 303 Y points at the last value that was stored on the stack. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 B7 76 translates to... TFR SP,Y S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 304 The content of X is unchanged. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 B7 57 translates to... TFR X,SP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 305 The content of Y is unchanged. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 B7 67 translates to... TFR Y,SP S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 306 – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 WAI (before interrupt) OSSSSsf OSSSfSsf WAI (when interrupt comes) fVfPPP VfPPP Although the WAI instruction itself does not alter the condition codes, the interrupt that causes the CPU to resume processing also causes the I mask bit (and the X mask bit, if the interrupt was XIRQ) to be set as the interrupt vector is fetched.
Page 307 – Z: 1; set H, N, V and C may be altered by this instruction Access Detail Address Source Form Object Code Mode HCS12 M68HC12 Special Of(frr,ffff)O Off(frr,fffff)O (replace comma if interrupted) 18 3C SSS + UUUrr SSSf + UUUrr 1.
Page 308 EXG D,X instruction by the assembler. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 XGDX B7 C5 translates to... EXG D,X S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 309 EXG D,Y instruction by the assembler. CCR Details: – – – – – – – – Access Detail Address Source Form Object Code Mode HCS12 M68HC12 XGDY B7 C6 translates to... EXG D,Y S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 310 Instruction Glossary S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 311: Section 7. Exception Processing
The six highest vector addresses are used for resets and unmaskable interrupt sources. The remaining vectors are used for maskable interrupts. All vectors must be programmed to point to the address of the appropriate service routine. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 312: Exception Priority
XIRQ signal $FFF2–$FFF3 IRQ signal $FF00–$FFF1 Device-specific interrupt sources (HCS12) $FFC0–$FFF1 Device-specific interrupt sources (M68HC12) 1. See Device User Guide and Interrupt Block Guide for further details The CPU12 can handle up to 128 exception vectors, but the number actually used varies from device to device, and some vectors are reserved for Freescale use.
Page 313: Resets
— the higher the address, the higher the priority of the interrupt. Other maskable interrupts are associated with on-chip peripherals such as timers or serial ports. On the HCS12, logic in the device integration module can give one I-masked source priority over other I-masked sources. Refer to the documentation for the specific HCS12 derivative for more information.
Page 314: Power-On Reset
7.4.1 Power-On Reset The HCS12 incorporate circuitry to detect a positive transition in the V supply and initialize the device during cold starts, generally by asserting the reset signal internally. The signal is typically released after a delay that allows the device clock generator to stabilize.
Page 315: Interrupts
7.5 Interrupts Each HCS12 device can recognize a number of interrupt sources. Each source has a vector in the vector table. The XIRQ signal, the unimplemented opcode trap, and the SWI instruction are non-maskable, and have a fixed priority. The remaining interrupt sources can be masked by the I bit. In most...
Page 316: Interrupt Recognition
At the end of the interrupt service routine, an RTI instruction restores context from the stacked registers, and normal program execution resumes. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 317: External Interrupts
The CPU12 uses the next address after an unimplemented page 2 opcode as a return address. This differs from the M68HC11 illegal opcode interrupt, which uses the address of an illegal opcode as the return address. In the S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 318: Software Interrupt Instruction (Swi)
(the CPU does not provide this address). After the vector fetch, the CPU selects one of the three alternate execution paths, depending upon the cause of the exception. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 319 SET I BIT IF XIRQ, SET X BIT 9.2 - P FETCH PROGRAM WORD 9.1 - P FETCH PROGRAM WORD FINISH FILLING INSTRUCTION QUEUE FINISH FILLING INSTRUCTION QUEUE Figure 7-1. Exception Processing Flow Diagram S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 320: Reset Exception Processing
16-bit word in the order B:A. This makes register order in the stack frame the same as that of the M68HC11, M6801, and the M6800. • Cycle 7.1/7.2 pushes the 16-bit word containing B:A onto the stack. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 321 • Cycle 9.1/9.2 is the third of three program word fetches that refill the instruction queue. It is the last cycle of exception processing. After this cycle the CPU starts executing the first cycle of the instruction at the head of the instruction queue. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 322 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 323: Section 8. Instruction Queue
The CPU12 uses an instruction queue to buffer program information and increase instruction throughput. The HCS12 implements the queue somewhat differently from the original M68HC12. The HCS12 queue consists of three 16-bit stages while the M68HC12 queue consists of two 16-bit stages, plus a 16-bit holding latch.
Page 324: Instruction Queue Status Signals
IPIPE0 and the high-order bit on IPIPE1. 8.3.1 HCS12 Timing Detail In the HCS12, data-movement information is available when E clock is high or on falling edges of the E clock; execution-start information is available when E clock is low or on rising edges of the E clock, as shown in Figure 8-1.
Page 325: M68Hc12 Timing Detail
DM0 REFERS TO DATA CAPTURED AT THE END OF CURRENT E-HIGH PERIOD Figure 8-1. Queue Status Signal Timing (HCS12) 8.3.2 M68HC12 Timing Detail In the M68HC12, data movement information is available on rising edges of the E clock; execution start information is available on falling edges of the E...
Page 326 No start Start interrupt sequence Start even instruction Start odd instruction 1. The HCS12 implementation does not include a holding latch, so these data movement codes are used only in the original M68HC12. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 327: Null (Code 0:0)
E cycle referred to by the ALD code. 8.3.6 ALL — Advance and Load from Latch (Code 1:1) This code is not used in the HCS12. In the M68HC12, the 2-stage instruction queue is advanced by one word and stage one is refilled with a word of program information from the buffer.
Page 328: Sev — Start Instruction On Even Address (Code 1:0)
8.4 Queue Reconstruction (for HCS12) The raw signals required for queue reconstruction are the address bus (ADDR), the data bus (DATA), the system clock (E), and the queue status signals (IPIPE1 and IPIPE2).
Page 329: Queue Reconstruction Registers (For Hcs12)
64-Kbyte address space. When memory expansion is used, expanded addresses must also be captured and maintained. 8.4.1 Queue Reconstruction Registers (for HCS12) Queue reconstruction requires the following registers, which can be implemented as software variables when previously captured trace data is used, or as hardware latches in real time.
Page 330: Reconstruction Algorithm (For Hcs12)
The SEV execution start code indicates that the reset vector pointed to an even address in this example. INSTRUCTION FIRST USER CYCLE CODES INSTRUCTION E CLOCK DATA BUS IPIPE[1:0] Figure 8-3. Reset Sequence for HCS12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 331: Queue Reconstruction (For M68Hc12)
8.5.1 Queue Reconstruction Registers (for M68HC12) Queue reconstruction requires these registers, which can be implemented as software variables when previously captured trace data is used or as hardware latches in real time. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 332: In_Add, In_Dat Registers
In the special case of a reset, there is a 5-cycle sequence (VfPPP) during which the reset vector is fetched and the instruction queue is filled, before execution of the first instruction begins. Due to the timing of the switchover S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 333: Lat Decoding
The previous contents of stage 1 are moved to stage 2, and the contents of the fetch buffer latch are transferred into stage 1 of the instruction queue. One or more cycles preceding the ALL S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 334 The SEV execution start code indicates that the reset vector pointed to an even address in this example. INSTRUCTION FIRST USER CYCLE CODES INSTRUCTION E CLOCK DATA BUS IPIPE[1:0] Figure 8-4. Reset Sequence for M68HC12 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 335: Instruction Tagging
Tagging is allowed in all modes. Tagging is disabled when BDM becomes active. Table 8-2. Tag Pin Function TAGHI TAGLO No tag Low byte High byte Both bytes S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 336 In HCS12 and M68HC12 derivatives that have hardware breakpoint capability, the breakpoint control logic and BDM control logic use the same internal signals for instruction tagging. The CPU does not differentiate between the two kinds of tags. The tag follows program information as it advances through the queue.
Page 337: Section 9. Fuzzy Logic Support
• REV (fuzzy logic rule evaluation) and REVW (fuzzy logic rule evaluation weighted), which perform unweighted or weighted MIN-MAX rule evaluation • WAV (weighted average), which performs weighted average defuzzification on singleton output membership functions. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 338: Fuzzy Logic Basics
Fuzzy logic has membership functions which emulate human concepts like “temperature is warm”; that is, conditions are perceived to have gradual boundaries. This concept seems to be a key element of the human ability to S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 339 INPUT MEMBERSHIP FUZZIFICATION FUNCTIONS FUZZY INPUTS … (IN RAM) RULE LIST RULE EVALUATION FUZZY OUTPUTS … (IN RAM) OUTPUT MEMBERSHIP DEFUZZIFICATION FUNCTIONS SYSTEM OUTPUTS Figure 9-1. Block Diagram of a Fuzzy Logic System S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 340: Fuzzification (Mem)
For example, the expression “temperature is warm” is 25 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 341 The end result of the fuzzification step is a table of fuzzy inputs representing current system conditions. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 342: Rule Evaluation (Rev And Revw)
The consequent portion of a rule is made up of one or more (in this case one) consequents. Each consequent expression consists of the name of a system output, followed by is, followed by a label name. Each consequent S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 343 (rule disabled) to one (rule fully enabled). The resulting modified truth value is then applied to the fuzzy outputs. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 344: Defuzzification (Wav)
RAM. If the system has more than one system output, the WAV instruction is executed once for each system output. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 345: Example Inference Kernel
Figure 9-3 is a complete fuzzy inference kernel written in CPU12 assembly language. Numbers in square brackets are cycle counts for an HCS12 device. The kernel uses two system inputs with seven labels each and one system output with seven labels. The program assembles to 57 bytes. It executes in about 20 µs at an 25-MHz bus rate.
Page 346 REV instruction takes 259 cycles, but it is interruptible so it does not cause a long interrupt latency. Lines 18 through 20 set up pointers and an iteration count for the WAV instruction. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 347: Mem Instruction Details
Alternatively, points and slopes for the membership functions can be determined and stored in memory with define-constant assembler directives. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 348 Typically, there are three to seven labels per system input, but there is no practical restriction on this number as far as the fuzzification step is concerned. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 349: Abnormal Membership Function Definitions
(Grade = $FF), or on the sloping portion of the right side of the trapezoid (Grade = Grade_2). 4b could still override this tentative value in grade. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 350 If the input was outside the trapezoid, flag_d12n would be one and grade_1 and grade_2 would have been forced to $00 in cycle 3. The else condition of 4b would set the result to $00. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 351: Abnormal Membership Function Case 1
If point_1 was to the right of point_2, flag_d12n would force the result to be $00 for all input values. In fact, flag_d12n always limits the region of interest to the space greater than or equal to point_1 and less than or equal to point_2. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 352: Abnormal Membership Function Case 2
In this case, 4a is not true, so grade equals grade_2. 4b is true because slope_1 is zero, so 4b does not overwrite grade. MEMORY DEFINITION: $60, $80, $00, $04; point_1, point_2, slope_1, slope_2 GRAPHICAL REPRESENTATION HOW INTERPRETED Figure 9-8. Abnormal Membership Function Case 3 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 353: Rev And Revw Instruction Details
After the REV instruction finishes, X will point at the next address past the $FF separator character that marks the end of the rule list. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 354 The V condition code bit should be one because the last element before the $FF end marker should have been a rule consequent. If V is zero after executing REV, it indicates the rule list was structured incorrectly. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 355: Interrupt Details
16-bit or no data is transferred. When a value is read from memory, it cannot be used by the CPU until the second cycle after the read takes place. This is due to access and propagation delays. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 356 $FE THEN A = MIN(A, F ELSE NO BUS ACCESS ELSE A = A (NO CHANGE TO A) = $FF (END OF RULES)? 7.0 - O READ PROGRAM WORD IF $3A MISALIGNED Figure 9-9. REV Instruction Flow Diagram S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 357 Y for this read, the previously read R is checked to see if it is a separator character ($FE). If R was $FE and the V bit was one, this indicates a switch S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 358 In cycle 6.2, the X index register is adjusted backward by one because the last rule byte needs to be re-fetched when the REV instruction resumes. After cycle 6.2, the REV instruction is finished, and execution would continue to the normal interrupt processing flow. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 359: Weighted Rule Evaluation (Revw)
$00. If these values are not initialized before executing the REVW instruction, results will be erroneous. The X index register is set to the address of the first element in the rule list (in the knowledge base). The REVW instruction automatically updates this S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 360 The V condition code bit should be one because the last element before the $FFFF end marker should have been a rule consequent. If V is zero after executing REVW, it indicates the rule list was structured incorrectly. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 361: Interrupt Details
(refer to Section 6. Instruction Glossary details). Lower case letters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate cycles where 16-bit data could be transferred. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 362 7.0 - O NO BUS ACCESS ADJUST PC TO POINT AT NEXT INSTRUCTION 8.2 - f IF C = 1 (WEIGHTS ENABLED), Y = TMP2 + 1 FINISH MULTIPLY Figure 9-10. REVW Instruction Flow Diagram S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 363 After all rules have been processed, cycle 7.0 is used to update the PC to point at the next instruction. If weights were enabled, Y is updated to point at the location that immediately follows the last rule weight. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 364: Wav Instruction Details
B is the iteration count n. The B accumulator must be set to the number of labels for this system output. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 365: Wav Interrupt Details
WAV instruction has been interrupted. This recovery operation is called the wavr pseudo-instruction. Figure 9-12 is a flow diagram of the WAV instruction in the HCS12, including the wavr pseudo-instruction. Figure 9-12 is a flow diagram of the WAV instruction in the M68HC12, including the wavr pseudo-instruction.
Page 366 READ PROGRAM WORD IF $3C MISALIGNED ADJUST PC TO POINT AT NEXT INSTRUCTION Y : D = TMP1 : TMP2; X = TMP3 Figure 9-11. WAV and wavr Instruction Flow Diagram (for HCS12) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 367 READ PROGRAM WORD IF $3C MISALIGNED ADJUST PC TO POINT AT NEXT INSTRUCTION Y : D = TMP3 : TMP2; X = TMP1 Figure 9-12. WAV and wavr Instruction Flow Diagram (for M68HC12) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 368 Upon normal completion of the instruction (cycle 10.0), the PC is adjusted so it points to the next instruction. The results are transferred from the TMP registers into CPU registers in such a way that the EDIV instruction can be S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 369: Custom Fuzzy Logic Programming
(byte for TBL and word for ETBL). In both cases, the B S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 370 A accumulator. When the table is exited, the corresponding y-value is in the A accumulator. Figure 9-13 shows one way to work with this type of table. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 371 Examine the human problem of stopping a car at an intersection. Rules such as “If intersection is close and speed is fast, apply brakes” might be used. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 372: Rule Evaluation Variations
RAM. To do this, use the instruction EMAXM 2,X+ ;process one rule consequent The M at the end of the mnemonic indicates that the result will replace the referenced memory operand. Again, indexed addressing is used. These two S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 373: Defuzzification Variations
Max defuzzification is not a good general choice because it only works for a subset of fuzzy logic applications. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 374 32-bit result takes only three 25-MHz cycles. The EMACS instruction uses 16-bit operands and accumulates the result in a 32-bit memory location, taking only 12 25-MHz cycles per iteration, including accessing all operands from memory and storing the result to memory. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 375: Appendix A. Instruction Reference
(USED IN BCD ARITHMETIC) MASK (DISABLE) XIRQ INTERRUPTS RESET OR XIRQ SET X, INSTRUCTIONS MAY CLEAR X BUT CANNOT SET X STOP DISABLE (IGNORE STOP OPCODES) RESET DEFAULT IS 1 Figure A-1. Programming Model S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 376: A.2 Stack And Memory Layout
$FFFA, $FFFB Computer Operating Properly (COP Watchdog Reset $FFF8, $FFF9 Unimplemented Opcode Trap $FFF6, $FFF7 Software Interrupt Instruction (SWI) $FFF4, $FFF5 XIRQ $FFF2, $FFF3 $FFC0–$FFF1 (M68HC12) Device-Speciﬁc Interrupt Sources $FF00–$FFF1 (HCS12) Device-Speciﬁc Interrupt Sources S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 377: A.4 Notation Used In Instruction Set Summary
— X or Y or SP xysp — X or Y or SP or PC Operators + — Addition – — Subtraction • — Logical AND — Logical OR (inclusive) Continued on next page S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 378 — Low-order byte of a 16-bit extended address. mm — 8-bit immediate mask value for bit manipulation instructions. Set bits indicate bits to be affected. pg — Program page (bank) number used in CALL instruction. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 379 , — Indicates where an interrupt could be honored Special Cases PPP/P — Short branch, PPP if branch taken, P if not OPPP/OPO — Long branch, OPPP if branch taken, OPO if not S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 380 ⇑ — Status bit may be set or remain cleared, but is not cleared by operation. ? — Status bit may be changed by operation but the final state is not defined. — Status bit used for a special purpose. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 381 Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 (A) + (B) ⇒ A – – ∆ – ∆ ∆ ∆ ∆ 18 06 Add Accumulators A and B (B) + (X) ⇒ X –...
Page 382 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 – – – – ∆ ∆ ∆ ∆ ASL opr16a 78 hh ll rPwO rOPw ASL oprx0_xysp 68 xb ASL oprx9,xysp...
Page 383 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 BLS rel8 Branch if Lower or Same – – – – – – – – 23 rr PPP/P PPP/P (if C...
Page 384 Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 – – – – ∆ ∆ ∆ ∆ CMPB #opr8i (B) – (M) C1 ii CMPB opr8a Compare Accumulator B with Memory...
Page 385 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 (M) – $01 ⇒ M ∆ ∆ ∆ – DEC opr16a – – – – 73 hh ll rPwO rOPw...
Page 386 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 (M:M+1)+ [(B)×((M+2:M+3) – (M:M+1))] ⇒ D ∆ ∆ – ∆ ETBL oprx0_xysp – – – – 18 3F xb ORRffffffP ORRffffffP...
Page 387 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 LBGT rel16 Long Branch if Greater Than – – – – – – – – 18 2E qq rr OPPP/OPO OPPP/OPO (N ⊕...
Page 388 Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 (M:M+1) ⇒ Y ∆ ∆ 0 – LDY #opr16i – – – – CD jj kk LDY opr8a Load Index Register Y...
Page 389 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 MIN((A), (M)) ⇒ A – – – – ∆ ∆ ∆ ∆ MINA oprx0_xysp 18 19 xb OrPf OrfP MINA oprx9,xysp...
Page 390 Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 ) ⇒ A; (SP) + 1 ⇒ SP PULA – – – – – – – – (SP) Pull Accumulator A from Stack ) ⇒...
Page 391 Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 (A) – (B) ⇒ A – – – – ∆ ∆ ∆ ∆ 18 16 Subtract B from A (A) – (M) – C ⇒ A –...
Page 392 Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 ) ⇒ M:M+1 ∆ ∆ 0 – STS opr8a – – – – 5F dd STS opr16a Store Stack Pointer...
Page 393 Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 (M) + [(B) × ((M+1) – (M))] ⇒ A ∆ ∆ – ∆ TBL oprx0_xysp – – – – 18 3D xb ORfffP...
Page 394 Table A-1. Instruction Set Summary (Sheet 14 of 14) Access Detail Addr. Machine Source Form Operation S X H I N Z V C Mode Coding (hex) HCS12 M68HC12 ? ∆ ? ? Special 18 3C – – ? – Of(frr,ffff)O Off(frr,fffff)O ∑ ∑ ⇒...
Page 395 ‡2-4 BSET BSET wavr BSET ‡2-4 BCLR BCLR BCLR ‡4-6 ‡†7 ‡2-4 BRSET BRSET BRSET ‡4-6 ‡2-4 BRCLR BRCLR BRCLR Key to Table A-2 Opcode Number of HCS12 cycles (‡ indicates HC12 different) Mnemonic BGND Address Mode Number of bytes...
Page 396 Table A-2. CPU12 Opcode Map (Sheet 2 of 2) MOVW IDIV LBRA TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP IM-ID MOVW FDIV LBRN TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP EX-ID...
Page 397 Table A-3. Indexed Addressing Mode Postbyte Encoding (xb) –16,X 1,+X 1,X+ –16,Y 1,+Y 1,Y+ 0,SP –16,SP 1,+SP 1,SP+ 0,PC –16,PC n,SP 5b const 5b const pre-inc post-inc 5b const 5b const pre-inc post-inc 5b const 5b const pre-inc post-inc 5b const 5b const 9b const 9b const...
Page 398 X, Y, SP, or PC 111rr011 [n,r] 16-bit offset indexed-indirect rr can specify X, Y, SP, or PC 111rr111 [D,r] Accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 399 Table A-5. Transfer and Exchange Postbyte Encoding TRANSFERS ⇓ LS MS⇒ A ⇒ A B ⇒ A CCR ⇒ A ⇒ A B ⇒ A ⇒ A ⇒ A ⇒ A TMP3 A ⇒ B B ⇒ B CCR ⇒ B ⇒...
Page 400 N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional For 16-bit offset long branches precede opcode with a $18 page prebyte. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 401 Table A-8. Hexadecimal to ASCII Conversion ASCII ASCII ASCII ASCII SP space grave “ quote & ‘ BEL beep apost. BS back HT tab linefeed , comma CR return dash period ESCAPE < > _ under delete S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 402: A.5 Hexadecimal To Decimal Conversion
Subtract the decimal number found from the original decimal number to get the remaining decimal value. Repeat the procedure using the remaining decimal value for each subsequent hexadecimal digit. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 403: Appendix B. M68Hc11 To Cpu12 Upgrade Path
• Same programming model • Same stacking operations • Upgrade to 16-bit architecture • Eliminate extra byte/extra cycle penalty for using index register Y • Improve performance • Improve compatibility with high-level languages S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 404: B.3 Source Code Compatibility
ABX and ABY are rarely used in new CPU12 LEAX B,X programs. ABX is one byte on M68HC11 but LEAY B,Y ABY is two bytes. The LEA substitutes are two bytes. Continued on next page S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 405 CPU12 opcode map. Object code for each of the moved instructions is one byte smaller than object code for the equivalent M68HC11 instruction. Table B-2 shows instructions that assemble to one byte less object code on the CPU12. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 406 It seems useful to mention the results of size comparisons done on C programs. A C program compiled for the CPU12 is about 30 percent smaller than the same program compiled for the M68HC11. The savings are largely due to better indexing. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 407: B.4 Programmer's Model And Stacking
16-bit pointers and to speed up math operations. B.5.1 Bus Structures The CPU12 is a 16-bit processor with 16-bit data paths. Typical HCS12 and M68HC12 devices have internal and external 16-bit data paths, but some derivatives incorporate operating modes that allow for an 8-bit data bus, so that a system can be built with low-cost 8-bit program memory.
Page 408: B.5.2 Instruction Queue
In this case, the O cycle appears as a free cycle since the queue is not ready to accept the next word of program information. If this same instruction had S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 409: B.5.3 Stack Function
SP twice. To illustrate, consider the operation of a PULX instruction. With the next-available M68HC11 stack, if the SP = $01F0 when execution begins, S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 410: B.6 Improved Indexing
Y-related indexing in the M68HC11 has been eliminated. In addition, high-level language requirements, including stack relative indexing and the ability to perform pointer arithmetic directly in the index registers, have been accommodated. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 411 Y index register, the object code is one byte smaller than it was for the M68HC11. Table A-3 Table A-4 summarize CPU12 indexed addressing mode capabilities. Table A-6 shows how the postbyte is encoded. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 412: B.6.1 Constant Offset Indexing
16-bit offset can be regarded as a signed (–32,768 to +32,767) or unsigned (0 to 65,535) value. In 16-bit constant offset mode, the offset is supplied in two extension bytes after the opcode and postbyte. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 413: B.6.2 Auto-Increment Indexing
3-instruction sequence because the Z condition code bit is affected by the M68HC11 INY instructions, while the Z bit in the CPU12 would be determined by the value loaded into A. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 414: B.6.3 Accumulator Offset Indexing
This reduces the loop execution time from 15 cycles to six cycles. This reduction, combined with the 25-MHz bus speed of the HCS12 (M68HC12) Family, can have significant effects. B.6.4 Indirect Indexing The CPU12 allows some forms of indexed indirect addressing where the instruction points to a location in memory where the address of the operand is stored.
Page 415: B.7 Improved Performance
B.7 Improved Performance The HCS12 uses a system-on-a-chip (SoC) design methodology and is normally implemented in a 0.25µ FLASH process. HCS12 devices can operate at up to 25 MHz and are designed to be migrated easily to faster, smaller silicon process technologies as they are developed.
Page 416: B.7.3 Code Size Reduction
In some specialized areas, the reduction is much greater. A fuzzy logic inference kernel requires about 250 bytes in the M68HC11, and the same program for the CPU12 requires about 50 bytes. The CPU12 fuzzy logic S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 417: B.8 Additional Functions
64-Kbyte address map for M68HC12 devices incorporating this feature. Table B-4 is a summary of these new instructions. Subsequent paragraphs discuss significant enhancements. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 418 Long branch if higher or same (same as LBCC) LBLE Relative Long branch if less than or equal to zero LBLO Relative Long branch if lower (same as LBCS) LBLS Relative Long branch if lower or same S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 419 Inherent Table lookup and interpolate (8-bit entries) TBNE Relative Test register and branch if not equal to zero (looping primitive) Inherent Transfer register contents to another register Special Weighted average (fuzzy logic support) S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 420: B.8.1 Memory-To-Memory Moves
CPU register and then branch based on a zero or non-zero test result. The CPU registers that can be used for the loop count are A, B, D, X, Y, or S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 421: B.8.4 Long Branches
Before this sequence is executed, the fuzzy outputs must be cleared to zeros (not shown). M68HC11 MIN or MAX operations are performed by executing a compare followed by a conditional branch around a load or store operation. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 422: B.8.6 Fuzzy Logic Support
750 milliseconds. The CPU12 kernel uses about 50 bytes and executes in about 16 microseconds (in a 25-MHz HCS12). B.8.7 Table Lookup and Interpolation The CPU12 instruction set includes two instructions (TBL and ETBL) for lookup and interpolation of compressed tables.
Page 423: B.8.8 Extended Bit Manipulation
LDX 5,SP+ loads X with the value on the bottom of the stack and deallocates five bytes from the stack in a single operation that takes only two bytes of object code. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 424: B.8.11 Support For Memory Expansion
Some HCS12 and M68HC12 variants include a built-in bank switching scheme that eliminates many of the problems associated with external switching logic. The CPU12 includes CALL and return-from-call (RTC) instructions that manage the interface to the bank-switching system.
Page 425: Appendix C. High-Level Language Support
Some of the higher math functions allow for division and multiplication involving 32-bit values, although it is somewhat less common to use such long values in a microcontroller system. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 426: C.3 Parameters And Variables
Adding PSHC and PULC improved orthogonality by completing the set of stacking instructions so that any of the CPU registers can be pushed or pulled. These instructions are also useful for preserving the CCR value during a function call subroutine. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 427: C.3.2 Allocating And Deallocating Stack Space
After the function subroutine finishes, calculations are required to restore the stack pointer to the S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 428: C.4 Increment And Decrement Operators
The most apparent case is the IDIVS instruction, which divides two 16-bit signed numbers to produce a 16-bit result. While the same function can be accomplished with the EDIVS instruction (a 32 by 16 divide), doing so is S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 429: C.6 Conditional If Constructs
D offset variation of indirect indexed addressing. C.8 Pointers The CPU12 supports pointers by allowing direct arithmetic operations on the 16-bit index registers (LEAS, LEAX, and LEAY instructions) and by allowing indexed indirect addressing modes. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 430: C.9 Function Calls
Push and pull instructions can be used to stack some or all the CPU registers during a function call. The CPU12 can push and pull any of the CPU registers A, B, CCR, D, X, Y, or SP. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 431: C.10 Instruction Set Orthogonality
Greater regularity of the instruction set makes it possible to implement compilers more efficiently, because operation is more consistent, and fewer special cases must be handled. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 432 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 433: Index
........... . . 114 ASLD S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 434 ..........53, 76, 137, Bit-condition S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 435 ............151 CLV instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 436 ........... . . 166 DECB instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 437 ......... .44, 50, 424, Expanded memory S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 438 ........328 HCS12 queue reconstruction .
Page 439 ..........41 Accumulator direct S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 440 ........... . JSR instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 441 ............77 Offset values S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 442 ........... 41 Move instructions S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 443 Orthogonality............431 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 444 ........328 HCS12 queue reconstruction .
Page 445 ..........324 HCS12 timing detail .
Page 446 ........50, 78, 144, 269, Expanded memory S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 447 ......... . . 61 Decrement and increment S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 448 ........68, 307, 337, 344, 364–368 WAV instruction S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 449 ............366 HCS12 .
Page 450 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor...
Page 452 Freescale Semiconductor assume any liability arising out of the application or use of any Japan: product or circuit, and speciﬁcally disclaims any and all liability, including without Freescale Semiconductor Japan Ltd.

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