Analog Devices EVAL-ADAU1850 User Manual page 6

User Guide
SETTING UP COMMUNICATION IN SOFTWARE
Configure the Register Control, FastDSP, and EQ settings on the
left navigation panel. Lark-Lite Register Control has multiple tabs
that control different sections of the ADAU1850.
the Power tab, which allows the user to power up or power down
various blocks within the ADAU1850. When a block is powered up,
that block can be configured.
The Clock tab allows the PLL to be used or bypassed. By regis-
ter default, the PLL is enabled but bypassed to save power. To
generate a 24.576 MHz master clock, enable or disable the PLL
according to the provided clock source. On the evaluation board, a
24.576 MHz oscillator is supplied.
To configure an application, follow these steps:
analog.com
1. Enable POWER_EN, MASTER_BLOCK_EN, and CM_START-
Figure 5 shows
2. With the default 24.576 MHz oscillator on board, set
3. Configure the other blocks.
When a register value is changed, click the related Write button in
a block to update a single register, or the Write this Page button
below the tabs to update multiple registers. Click Write All after all
register changes to avoid a configuration error.
Figure 5. Register Configuration
EVAL-ADAU1850
UP_OVER in the CHIP_PWR block in the Power tab by clicking
the OFF button to switch to ON (see
on-board 24.576 MHz oscillator is used, ensure MCLKIN_EN is
enabled in the Clock tab.
PLL_FM_BYPASS to PLL_FM_BP in the Clock tab.
Figure 5). When an
Rev. A | 6 of 12