Other Interfaces; Wlan_Slp_Clk; Sdio_Vsel - Quectel FC80A User Manual

The following figure shows the PCM interface connection between FC80A and the host.

3.6. Other Interfaces

3.6.1. WLAN_SLP_CLK

The 32.768 kHz sleep clock is used in low power modes, such as power saving mode and sleep mode. It
serves as a timer to determine when to wake up FC80A to receive signals in various power saving
schemes, and to maintain basic logic operations when the module is in sleep mode.
Table 13: Pin Definition of WLAN_SLP_CLK Interface
Pin Name Pin No.
WLAN_SLP_CLK 31

3.6.2. SDIO_VSEL

SDIO voltage domain can be selected through SDIO_VSEL. The following table shows the pin definition
of SDIO_VSEL.
Table 14: Pin Definition of SDIO_VSEL
Pin Name Pin No.
SDIO_VSEL 24
FC80A_Hardware_Design
PCM_CLK
PCM_SYNC
FC80A
PCM_DOUT
PCM_DIN
Figure 8: PCM Interface Connection
I/O Description
External 32.768 kHz low power
DI
clock input
I/O Description
SDIO voltage select
DI pull down: 3.3 V
pull up: 1.8 V
Wi-Fi&Bluetooth Module Series
PCM_CLK
PCM_SYNC
Host
PCM_DIN
PCM_DOUT
Comment
Comment
1.8 V or 3.3 V power domain.
Pull up to VDDIO internally through a
200 kΩ resistor, high level by default.
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