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After the above sequence D5, 6, 9, 10, 15, 16,17, 18 will flash together (Figure 2)
Evaluating the Results
The sequential illumination of the LEDs indicate the successful writing of the core registers using the user master of the
microprocessor interface. States 1 and 2 unlock the core registers. State 3 writes to the loop back register, and the remaining
states indicate the initialization of the eight channels.
The evaluation design uses an external primary input connected to SW3.1 to enable and disable the internal(near-end) and
external(far end) loop back modes. With SW3.1 in the "off" position near-end loop back is enabled. When the LED array is
flashing as depicted in Figure 2, this indicated successful internal loop back traffic.
For evaluating far-end loop back the following DIP switches must be in the position shown in Figure 4.
SW6,SW7,SW8,SW9,SW10,SW11,SW12,SW13,SW14,SW15,SW16,SW17,SW18,SW9,SW20,SW21,SW22,SW23,SW24
,SW25,SW26,SW27,SW28,SW29,SW30,SW31,SW32SW33,SW34,SW35,SW36,SW37
A cable( W.L. Gore P/N 2MMA3106-00) not provided with the evaluation kit can be used to make an external connection
between CON 4 and CON3. This external connection will successfully loop back 8 channels when SW3.1 is in the ON
position(loop back disabled).
CON4 and CON3 can also be used to observe the signal integrity of the ORT8850 LVDS channels. A cable similar to one
from W.L Gore P/N 2MMA3143-01 adapts the 2mm Z-Pack to individual SMA connectors and is useful to observe the
LVDS channels or connect to other test devices.
For cable information visit
Figure 1
1
5
2
6
3
7
4
8
Figure 4
(http://www.wlgore.com/
).
Lattice Semiconductor Corp. - -Proprietary
Use Pursuant to Company Instructions
Figure 2
Page 3
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