Tews Technologies TAMC640-10R Manuals

Manuals and User Guides for Tews Technologies TAMC640-10R. We have 1 Tews Technologies TAMC640-10R manual available for free PDF download: User Manual

Tews Technologies TAMC640-10R User Manual (69 pages)

Virtex-5 AMC with FMC Slot

Brand: Tews Technologies | Category: I/O Systems | Size: 1 MB

Table of Contents
4
Product Description
8
Figure 1-1 : Block Diagram
9
Technical Specification
10
Table 2-1 : Technical Specification
11
Handling and Operation Instruction
12
ESD Protection
12
Thermal Considerations
12
MID-Size Option Usage Restrictions
12
I/O Signaling Voltages
12
Voltage Limits on Fmcs
12
Ipmi Support
13
Temperature and Voltage Sensors
13
Sensor Locations
13
Figure 4-1 : Temp. Sensor Locations
13
Table 4-1 : Temperature and Voltage Sensors
13
FRU Information
14
Internal Use Area
14
Table 4-2 : Fru Information
14
Table 4-3 : Internal Use Area
14
Board Info Area
15
Product Info Area
15
Table 4-4 : Board Info Area
15
Table 4-5 : Product Info Area
15
Multi Record Area
16
Module Current Requirements
16
AMC Point-To-Point Connectivity
16
Table 4-6 : Module Current Requirement (W/O Fmc)
16
Clock Configuration
17
Modifying FRU Records
17
Table 4-7 : Amc Point-To-Point Connectivity
17
Table 4-8 : Clock Configuration
17
Functional Description
18
Figure 5-1 : Tamc640 Functional Block Diagram
18
Table 5-1 : Tamc640 Fpga Feature Overview
19
Table 5-2 : Fpga Bank Usage
19
AMC Interface
20
FMC Interface
20
Figure 5-2 : Amc Interface Diagram
20
Figure 5-3 : Fmc Interface to Virtex-5 Fpga
21
Table 5-3: Fmc-Supplies
21
Vadj
22
Memory Interfaces
22
SPI-Flash
22
Figure 5-4 : a Fmc Module
22
Qdr-II Sram
23
Ddr2 Sdram
23
Figure 5-5 : Qdr-II Sram Interface to Fpga
23
Reset
24
Figure 5-6 : Ddr2 Sdram Interfaces to Fpga
24
Figure 5-7 : Reset Structure
24
Gpio
25
I 2 C
25
Table 5-4 : General Purpose I/O
25
Table 5-5 : I2C Bus Signals
25
Uart
26
Figure 5-8 : I2C Bus Structure Overview
26
Table 5-6 : Fpga Uart
26
Multi-Gigabit Transceiver (Gtps)
27
Figure 5-9 : Gtp Block Diagram
27
Configuration
28
Board Configuration CPLD (BCC)
28
Figure 5-10: Board Configuration Cpld Block Diagram
28
FPGA Configuration
29
Table 5-7 : Worst Case Fpga Configuration Times
30
Clock Configuration
31
Table 5-8 : Tclk Transceiver Configuration
31
Table 5-9 : Jitter Attenuator Configuration
31
Figure 5-11: Clock Configuration
32
Clocks
33
Figure 5-12: Fpga Clock Sources
33
GTP Reference Clock Generator
34
Table 5-10: Available Fpga Clocks
34
Jtag
35
Figure 5-13: Jtag-Chain Segmentation
35
Table 5-11: Programmable Gtp Reference Clock
35
Thermal Management
36
Table 5-12: Configuration Dip-Switch Sw1-Sw2 Settings
36
Board Configuration
37
Overview
37
DIP-Switch
37
Figure 6-1 : Pre-Insertion Board Configuration Overview
37
Table 6-1 : Dip-Switch
37
Battery
38
Debug Connector
38
Installation
39
Installation of a FMC Module
39
Using Fmcs with MID-Size Faceplates
39
Voltage Limits on FMC Modules
39
Figure 7-1 : Using Fmcs with MID-Size Faceplates
39
Table 7-1 : Voltage Limits on Fmc Modules
39
AMC Module Insertion & Hot-Swap
40
Insertion
40
Extraction
40
Table 7-2 : Hot-Swap States
40
Indicators
41
Front Panel Leds
41
On Board Leds
41
Figure 8-1 : Front Panel Led View
41
Figure 8-2 : on Board Led View
41
Table 8-1 : Front Panel Leds
41
Table 8-2 : Board-Status Leds
42
O Connectors
43
Overview
43
I/O Circuitry
43
Differential Signaling
43
Figure 9-1: Connector Positions - Side 1
43
Figure 9-2: Connector Position - Side 2
43
AMC-Connector X4
44
Table 9-1: Pin Assignment Amc Connector X4
45
FMC HPC Connector X2
46
Table 9-2: Pin Assignment Fmc-Connector X2 Row F-K
47
Table 9-3: Pin Assignment Fmc-Connector X2 Row A-E
48
Debug-Connector X1
49
Table 9-4: Pin Assignment Debug Connector X1
49
Design Help
50
GTP Reference Clock Generator Configuration
50
Example Design
50
Troubleshooting
51
Board Does Not Power up
51
DONE Is Always off
51
INIT LED Stays Illuminated (Red)
51

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