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LPC11E37HFBD64/401
NXP Semiconductors LPC11E37HFBD64/401 Manuals
Manuals and User Guides for NXP Semiconductors LPC11E37HFBD64/401. We have
1
NXP Semiconductors LPC11E37HFBD64/401 manual available for free PDF download: User Manual
NXP Semiconductors LPC11E37HFBD64/401 User Manual (424 pages)
Brand:
NXP Semiconductors
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Chapter 1: Lpc11Exx Introductory Information
5
Introduction
5
Features
5
Ordering Information
8
Block Diagram
9
Table of Contents
11
How to Read this Chapter
11
Memory Map
11
Chapter 2: Lpc11Exx Memory Mapping
12
Chapter 3: Lpc11Exx System Control Block
14
How to Read this Chapter
14
Introduction
14
Pin Description
14
Clocking and Power Control
14
Register Description
15
System Memory Remap Register
17
Peripheral Reset Control Register
18
System PLL Control Register
18
System PLL Status Register
19
System Oscillator Control Register
19
Watchdog Oscillator Control Register
20
Internal Resonant Crystal Control Register
21
System Reset Status Register
21
System PLL Clock Source Select Register
21
System PLL Clock Source Update Register
22
Main Clock Source Select Register
22
Main Clock Source Update Enable Register
22
System Clock Divider Register
23
System Clock Control Register
23
SSP0 Clock Divider Register
25
USART Clock Divider Register
26
SSP1 Clock Divider Register
26
CLKOUT Clock Source Select Register
26
CLKOUT Clock Source Update Enable Register
27
CLKOUT Clock Divider Register
27
POR Captured PIO Status Register 0
27
POR Captured PIO Status Register 1
28
BOD Control Register
28
System Tick Counter Calibration Register
29
IRQ Latency Register
29
NMI Source Selection Register
29
Pin Interrupt Select Registers
30
Interrupt Wake-Up Enable Register 0
30
Interrupt Wake-Up Enable Register 1
31
Deep-Sleep Mode Configuration Register
32
Wake-Up Configuration Register
32
Power Configuration Register
33
Device ID Register
34
Flash Memory Access
35
Reset
35
Start-Up Behavior
36
Brown-Out Detection
36
Power Management
37
Reduced Power Modes and WWDT Lock Features
37
Active Mode
38
Power Configuration in Active Mode
38
Sleep Mode
38
Power Configuration in Sleep Mode
38
Programming Sleep Mode
39
Wake-Up from Sleep Mode
39
Deep-Sleep Mode
39
Power Configuration in Deep-Sleep Mode
39
Programming Deep-Sleep Mode
39
Wake-Up from Deep-Sleep Mode
40
Power-Down Mode
40
Power Configuration in Power-Down Mode
41
Programming Power-Down Mode
41
Wake-Up from Power-Down Mode
41
Deep Power-Down Mode
42
Mode
42
Programming Deep Power-Down Mode
42
Wake-Up from Deep Power-Down Mode
43
System PLL Functional Description
43
Lock Detector
44
Power-Down Control
44
Divider Ratio Programming
44
Post Divider
44
Feedback Divider
44
Changing the Divider Values
44
Frequency Selection
44
Normal Mode
45
Power-Down Mode
45
Chapter 4: Lpc11Exx Power Management Unit (PMU)
46
How to Read this Chapter
46
Introduction
46
Register Description
46
Power Control Register
46
General Purpose Registers 0 to 3
47
General Purpose Register 4
47
Functional Description
48
Chapter 5: Lpc11Exx Power Profiles
49
How to Read this Chapter
49
Features
49
Basic Configuration
49
General Description
49
Definitions
50
Clocking Routine
51
Set_Pll
51
Param0: System PLL Input Frequency and Param1: Expected System Clock
52
Param2: Mode
52
Param3: System PLL Lock Time-Out
52
Code Examples
53
Invalid Frequency
53
Exceeded)
53
Invalid Frequency Selection
53
Restrictions)
53
Exact Solution Cannot be Found (PLL)
53
Value
54
Expected Value
54
Power Routine
54
Set_Power
54
Pwr_Default
56
Pwr_Cpu_Performance
56
Pwr_Efficiency
56
Pwr_Low_Current
56
Pwr_Invalid_Freq
56
Param0: Main Clock
56
Param1: Mode
56
Param2: System Clock
56
Code Examples
56
Exceeded)
56
Chapter 6: Lpc11Exx NVIC
58
How to Read this Chapter
58
Introduction
58
Features
58
Interrupt Sources
58
Register Description
60
Interrupt Set Enable Register 0 Register
61
Interrupt Clear Enable Register 0
62
Interrupt Set Pending Register 0 Register
63
Interrupt Clear Pending Register 0 Register
64
Interrupt Active Bit Register 0
65
Interrupt Priority Register 0
66
Interrupt Priority Register 1
67
Interrupt Priority Register 2
67
Interrupt Priority Register 3
67
Interrupt Priority Register 4
68
Interrupt Priority Register 5
68
Interrupt Priority Register 6
68
Interrupt Priority Register 7
69
Chapter 7: Lpc11Exx I/O Configuration
70
How to Read this Chapter
70
Introduction
70
General Description
70
Pin Function
71
Pin Mode
71
Hysteresis
72
Input Inverter
72
Input Glitch Filter
72
Open-Drain Mode
72
Analog Mode
72
C Mode
72
RESET Pin (Pin RESET_PIO0_0)
73
WAKEUP Pin (Pin PIO0_16)
73
Register Description
74
I/O Configuration Registers
76
RESET_PIO0_0 Register
76
PIO0_1 Register
77
PIO0_2 Register
78
PIO0_3 Register
78
PIO0_4 Register
79
PIO0_5 Register
79
PIO0_6 Register
80
PIO0_7 Register
81
PIO0_8 Register
81
PIO0_9 Register
82
SWCLK_PIO0_10 Register
83
TDI_PIO0_11 Register
84
TMS_PIO0_12 Register
85
PIO0_13 Register
86
TRST_PIO0_14 Register
87
SWDIO_PIO0_15 Register
88
PIO0_16 Register
89
PIO0_17 Register
90
PIO0_18 Register
90
PIO0_19 Register
91
PIO0_20 Register
92
PIO0_21 Register
93
PIO0_22 Register
93
PIO0_23 Register
94
PIO1_0 Register
95
PIO1_1 Register
96
PIO1_2 Register
97
PIO1_3 Register
97
PIO1_4 Register
98
PIO1_5 Register
99
PIO1_6 Register
99
PIO1_7 Register
100
PIO1_8 Register
101
PIO1_9 Register
102
PIO1_10 Register
102
PIO1_11 Register
103
PIO1_12 Register
104
PIO1_13 Register
104
PIO1_14 Register
105
PIO1_15 Register
106
PIO1_16 Register
107
PIO1_17 Register
107
PIO1_18 Register
108
PIO1_19 Register
109
PIO1_20 Register
110
PIO1_21 Register
110
PIO1_22 Register
111
PIO1_23 Register
112
PIO1_24 Register
113
PIO1_25 Register
113
PIO1_26 Register
114
PIO1_27 Register
115
PIO1_28 Register
115
PIO1_29 Register
116
PIO1_31 Register
117
Chapter 8: Lpc11Exx Pin Configuration
118
How to Read this Chapter
118
Pin Configuration
118
Lpc11E12Fbd48/201
120
Lpc11E13Fbd48/301
120
Lpc11E14Fbd48/401
120
Lpc11E37Fbd48/501
120
See Table
121
Lpc11E36Fbd64/501
121
Lpc11E37Hfbd64/401
121
Lpc11E37Fbd64/501
121
Lpc11Exx Pin Description
121
Chapter 9: Lpc11Exx GPIO
129
How to Read this Chapter
129
Basic Configuration
129
Features
129
GPIO Pin Interrupt Features
129
GPIO Group Interrupt Features
129
GPIO Port Features
130
Introduction
130
GPIO Pin Interrupts
130
GPIO Group Interrupt
130
GPIO Port
130
Register Description
130
GPIO Pin Interrupts Register Description
133
Pin Interrupt Mode Register
133
Pin Interrupt Level (Rising Edge) Interrupt Enable Register
133
Pin Interrupt Level (Rising Edge) Interrupt Set Register
133
Pin Interrupt Level (Rising Edge Interrupt) Clear Register
134
Pin Interrupt Active Level (Falling Edge) Interrupt Enable Register
134
Pin Interrupt Active Level (Falling Edge) Interrupt Set Register
135
Pin Interrupt Active Level (Falling Edge Interrupt) Clear Register
135
Pin Interrupt Rising Edge Register
136
Pin Interrupt Falling Edge Register
136
Pin Interrupt Status Register
137
GPIO GROUP0/GROUP1 Interrupt Register Description
137
Grouped Interrupt Control Register
137
GPIO Grouped Interrupt Port Polarity Registers
137
GPIO Grouped Interrupt Port Enable Registers
138
GPIO Port Register Description
139
GPIO Port Byte Pin Registers
139
GPIO Port Word Pin Registers
139
GPIO Port Direction Registers
140
GPIO Port Mask Registers
140
GPIO Port Pin Registers
141
GPIO Masked Port Pin Registers
141
GPIO Port Set Registers
142
GPIO Port Clear Registers
142
GPIO Port Toggle Registers
142
Functional Description
143
Reading Pin State
143
GPIO Output
143
Masked I/O
144
GPIO Interrupts
144
Pin Interrupts
144
Group Interrupts
145
Recommended Practices
145
How to Read this Chapter
146
Basic Configuration
146
Features
146
Pin Description
146
Register Description
147
USART Receiver Buffer Register (When DLAB = 0, Read Only)
149
USART Transmitter Holding Register (When DLAB = 0, Write Only)
149
USART Divisor Latch LSB and MSB Registers (When DLAB = 1)
149
USART Interrupt Enable Register
150
Dlab = 0)
150
Only)
151
USART FIFO Control Register (Write Only) . 153 USART Line Control Register
154
USART Modem Control Register
155
Auto-Flow Control
155
Auto-RTS
155
Auto-CTS
156
USART Line Status Register (Read-Only)
157
USART Modem Status Register
159
USART Scratch Pad Register
159
USART Auto-Baud Control Register
160
Auto-Baud
160
Auto-Baud Modes
161
Irda Control Register
162
USART Fractional Divider Register
164
Baud Rate Calculation
165
Example 2: UART_PCLK = 12.0 Mhz, BR = 115200
167
USART Oversampling Register
167
USART Transmit Enable Register
168
UART Half-Duplex Enable Register
169
Smart Card Interface Control Register
169
USART RS485 Control Register
170
USART RS-485 Address Match Register
171
USART RS-485 Delay Value Register
171
USART Synchronous Mode Control Register 172 Functional Description
174
RS-485/EIA-485 Modes of Operation
174
RS-485/EIA-485 Normal Multidrop Mode
174
Mode
174
RS-485/EIA-485 Auto Direction Control
175
RS485/EIA-485 Driver Delay Time
175
RS485/EIA-485 Output Inversion
175
Smart Card Mode
175
Smart Card Set-Up Procedure
176
Architecture
177
Chapter 11: Lpc11Exx SSP/SPI
179
How to Read this Chapter
179
Basic Configuration
179
Features
179
General Description
179
Pin Description
180
Register Description
180
SSP/SPI Control Register 0
181
SSP/SPI Control Register 1
182
SSP/SPI Data Register
183
SSP/SPI Status Register
184
SSP/SPI Clock Prescale Register
184
SSP/SPI Interrupt Mask Set/Clear Register
184
SSP/SPI Raw Interrupt Status Register
185
SSP/SPI Masked Interrupt Status Register
185
SSP/SPI Interrupt Clear Register
186
Functional Description
186
Texas Instruments Synchronous Serial Frame Format
186
SPI Frame Format
187
Clock Polarity (CPOL) and Phase (CPHA) Control
187
SPI Format with CPOL=0,CPHA=0
188
SPI Format with CPOL=0,CPHA=1
189
SPI Format with CPOL = 1,CPHA = 0
189
SPI Format with CPOL = 1,CPHA = 1
191
Semiconductor Microwire Frame Format
191
Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
193
Chapter 12: Lpc11Exx I2C-Bus Controller
194
How to Read this Chapter
194
Basic Configuration
194
Features
194
Applications
194
General Description
194
I 2 C Fast-Mode Plus
195
Pin Description
196
Register Description
196
C Control Set Register (CONSET)
197
I 2 C Status Register (STAT)
199
I 2 C Data Register (DAT)
199
I 2 C Slave Address Register 0 (ADR0)
200
C SCL HIGH and LOW Duty Cycle Registers (SCLH and SCLL)
200
Selecting the Appropriate I C Data Rate and Duty Cycle
200
I 2 C Control Clear Register (CONCLR)
201
I 2 C Monitor Mode Control Register (MMCTRL)
201
Interrupt in Monitor Mode
202
Loss of Arbitration in Monitor Mode
203
I 2 C Slave Address Registers (ADR[1, 2, 3])
203
I 2 C Data Buffer Register (DATA_BUFFER)
203
NXP Semiconductors N.V. 2016. All Rights Reserved
203
C Mask Registers (MASK[0, 1, 2, 3])
204
Functional Description
204
Input Filters and Output Stages
205
Address Registers, ADR0 to ADR3
206
Address Mask Registers, MASK0 to MASK3
206
Comparator
206
Shift Register, DAT
206
Arbitration and Synchronization Logic
206
Serial Clock Generator
207
Timing and Control
208
Control Register, CONSET and CONCLR
208
Status Decoder and Status Register
208
I 2 C Operating Modes
208
Master Transmitter Mode
208
Master Receiver Mode
209
Slave Receiver Mode
210
Slave Transmitter Mode
211
Details of I 2 C Operating Modes
211
Master Transmitter Mode
212
Master Receiver Mode
216
Slave Receiver Mode
219
Slave Transmitter Mode
223
Miscellaneous States
225
STAT = 0Xf8
225
STAT = 0X00
225
Some Special Cases
226
Simultaneous Repeated START Conditions from
226
Two Masters
226
Data Transfer after Loss of Arbitration
227
Forced Access to the I C-Bus
227
C-Bus Obstructed by a LOW Level on SCL or SDA
228
Bus Error
228
C State Service Routines
228
Initialization
229
C Interrupt Service
229
The State Service Routines
229
Adapting State Services to an Application
229
Software Example
229
Initialization Routine
229
Start Master Transmit Function
229
Start Master Receive Function
230
I 2 C Interrupt Routine
230
Non Mode Specific States
230
State: 0X00
230
Master States
230
State: 0X08
230
State: 0X10
231
Master Transmitter States
231
State: 0X18
231
State: 0X20
231
State: 0X28
231
State: 0X30
232
State: 0X38
232
Master Receive States
232
State: 0X40
232
State: 0X48
232
State: 0X50
232
State: 0X58
233
Slave Receiver States
233
State: 0X60
233
State: 0X68
233
State: 0X70
233
State: 0X78
234
State: 0X80
234
State: 0X88
234
State: 0X90
234
State: 0X98
235
State: 0Xa0
235
Slave Transmitter States
235
State: 0Xa8
235
State: 0Xb0
235
State: 0Xb8
235
State: 0Xc0
236
State: 0Xc8
236
How to Read this Chapter
237
Basic Configuration
237
Features
237
Applications
238
General Description
238
Pin Description
238
Register Description
238
Interrupt Register
241
Timer Control Register
241
Timer Counter
242
Prescale Register
242
Prescale Counter Register
242
Match Control Register
243
Match Registers
244
Capture Control Register
244
Capture Registers
246
External Match Register
247
Count Control Register
248
PWM Control Register
251
Rules for Single Edge Controlled PWM Outputs
252
Example Timer Operation
253
Architecture
253
How to Read this Chapter
255
Basic Configuration
255
Features
255
Applications
256
General Description
256
Pin Description
256
Register Description
256
Interrupt Register
259
Timer Control Register
259
Timer Counter Registers
260
Prescale Register
260
Prescale Counter Register
260
Match Control Register
261
Match Registers
262
Capture Control Register
262
Capture Registers
264
External Match Register
264
Count Control Register
266
PWM Control Register
268
Rules for Single Edge Controlled PWM Outputs
269
Example Timer Operation
270
Architecture
271
Chapter 15: Lpc11Exx Windowed Watchdog Timer (WWDT)
273
How to Read this Chapter
273
Basic Configuration
273
Features
273
Applications
274
Description
274
Block Diagram
274
Clocking and Power Control
275
Using the WWDT Lock Features
276
Accidental Overwrite of the WWDT Clock
276
Changing the WWDT Clock Source
276
Changing the WWDT Reload Value
276
Register Description
277
Watchdog Mode Register
277
Watchdog Timer Constant Register
279
Watchdog Feed Register
279
Watchdog Timer Value Register
280
Watchdog Clock Select Register
280
Watchdog Timer Warning Interrupt Register . 280 Watchdog Timer Window Register
281
Watchdog Timing Examples
281
Chapter 16: Lpc11Exx System Tick Timer
283
How to Read this Chapter
283
Basic Configuration
283
Features
283
General Description
283
Register Description
284
System Timer Control and Status Register
284
System Timer Reload Value Register
285
System Timer Current Value Register
285
System Timer Calibration Value Register
286
Functional Description
286
Example Timer Calculations
286
Example (System Clock = 50 Mhz)
286
How to Read this Chapter
287
Basic Configuration
287
Features
287
Pin Description
287
Register Description
288
A/D Control Register (CR - 0X4001 C000)
289
A/D Global Data Register (GDR - 0X4001 C004)
290
A/D Interrupt Enable Register
291
0X4001 C00C)
291
A/D Data Registers
291
To 0X4001 C02C)
291
A/D Status Register (STAT - 0X4001 C030) . 291 Operation
292
Hardware-Triggered Conversion
292
Interrupts
292
Accuracy Vs. Digital Receiver
292
Top 64 Byte Are Reserved for 4 Kb EEPROM
293
How to Read this Chapter
293
Features
293
Basic Configuration
293
Description
293
Register Description
294
How to Read this Chapter
295
Bootloader
295
Features
295
General Description
296
Memory Map after any Reset
296
Flash Content Protection Mechanism
296
Criterion for Valid User Code
297
ISP/IAP Communication Protocol
298
ISP Command Format
298
ISP Response Format
298
ISP Data Format
298
ISP Flow Control
298
ISP Command Abort
298
Interrupts During ISP
298
Interrupts During IAP
299
RAM Used by ISP Command Handler
299
RAM Used by IAP Command Handler
299
Boot Process Flowchart
300
Sector Numbers
301
Lpc11E1X
301
Lpc11E3X
301
Code Read Protection (CRP)
302
ISP Entry Protection
304
ISP Commands
305
Unlock <Unlock Code
305
Set Baud Rate <Baud Rate> <Stop Bit
306
Echo <Setting
306
Write to RAM <Start Address> <Number of Bytes
306
Read Memory <Address> <No. of Bytes
307
Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number
307
Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes
308
Go <Address> <Mode
309
Sector Number
310
Lpc11E11Fhn33/101
311
Lpc11E14Fhn33/401
311
Lpc11E14Fbd64/401
311
Lpc11E35Fhi33/501
311
Lpc11E36Fhn33/501
311
Blank Check Sector(S) <Sector Number> <End
311
Sector Number
311
Read Part Identification Number
311
Return Code CMD_SUCCESS
312
Addr_Error
312
Addr_Not_Mapped
312
Param_Error
312
Read Boot Code Version Number
312
Compare <Address1> <Address2
312
No of Bytes
312
Readuid
312
Code_Read_Protection_Enabled
313
ISP Return Codes
313
IAP Commands
313
Prepare Sector(S) for Write Operation
315
Invalid_Sector
316
Sector_Not_Prepared_For_Write_Operation
316
Cmd_Success
316
Src_Addr_Error
316
Dst_Addr_Error
316
Src_Addr_Not_Mapped
316
Dst_Addr_Not_Mapped
316
Count_Error
316
Copy RAM to Flash
316
Erase Sector(S)
317
Blank Check Sector(S)
317
Read Part Identification Number
317
Compare_Error
318
Addr_Error
318
Addr_Not_Mapped
318
Read Boot Code Version Number
318
Compare <Address1> <Address2> <No of Bytes
318
Reinvoke ISP
318
Readuid
319
Erase Page
319
Write EEPROM
319
Invalid Command
320
Destination Address Is Not on a Correct Boundary
320
Source Address Is Not Mapped in the Memory Map
320
Count Value Is Taken in to Consideration Where Applicable
320
Read EEPROM
320
IAP Status Codes
320
Debug Notes
320
Comparing Flash Images
320
Serial Wire Debug (SWD) Flash Programming Interface
321
Register Description
321
EEPROM BIST Start Address Register
321
EEPROM BIST Stop Address Register
322
EEPROM Signature Register
322
Flash Controller Registers
323
Flash Memory Access Register
323
Flash Signature Generation
323
Signature Generation Address and Control
323
Registers
323
Signature Generation Result Registers
324
Flash Module Status Register
325
Flash Module Status Clear Register
325
Algorithm and Procedure for Signature
325
Generation
325
Signature Generation
325
Content Verification
326
How to Read this Chapter
327
Features
327
Introduction
327
Description
327
Pin Description
327
Functional Description
328
Debug Limitations
328
Debug Connections for SWD
328
Boundary Scan
329
How to Read this Chapter
330
Features
330
Description
330
Examples
331
Initialization
331
Signed Division
331
Unsigned Division with Remainder
332
How to Read this Chapter
333
Features
333
Basic Configuration
333
Description
333
Register Description
333
Examples
333
I/O Handler Software Library Applications
333
I/O Handler I S
334
I/O Handler UART
334
I/O Handler I 2 C
334
I/O Handler DMA
334
Chapter 23: Lpc11Exx Appendix Arm Cortex-M0
335
Introduction
335
About the Cortex-M0 Processor and Core Peripherals
335
System-Level Interface
336
Integrated Configurable Debug
336
Cortex-M0 Processor Features Summary
336
Cortex-M0 Core Peripherals
336
Processor
337
Programmers Model
337
Processor Modes
337
Stacks
337
Core Registers
337
General-Purpose Registers
338
Stack Pointer
338
Link Register
339
Program Counter
339
Program Status Register
339
Exception Mask Register
341
CONTROL Register
341
Exceptions and Interrupts
342
Data Types
342
The Cortex Microcontroller Software Interface Standard
342
Memory Model
343
Memory Regions, Types and Attributes
344
Memory System Ordering of Memory Accesses
345
Behavior of Memory Accesses
345
Software Ordering of Memory Accesses
346
Memory Endianness
347
Little-Endian Format
347
Exception Model
347
Exception States
347
Exception Types
348
Exception Handlers
349
Vector Table
349
Exception Priorities
350
Exception Entry and Return
351
Exception Entry
351
Exception Return
352
Fault Handling
353
Lockup
353
Power Management
354
Entering Sleep Mode
354
Wait for Interrupt
354
Wait for Event
354
Sleep-On-Exit
355
Wake-Up from Sleep Mode
355
Wake-Up from WFI or Sleep-On-Exit
355
Wake-Up from WFE
355
Power Management Programming Hints
355
Instruction Set
355
Instruction Set Summary
355
Intrinsic Functions
358
About the Instruction Descriptions
359
Operands
359
Restrictions When Using PC or SP
359
Shift Operations
360
Asr
360
Lsr
360
Lsl
361
Ror
361
Address Alignment
362
PC-Relative Expressions
362
Conditional Execution
362
The Condition Flags
363
Condition Code Suffixes
363
Memory Access Instructions
364
Adr
364
Syntax
364
Operation
364
Restrictions
365
Condition Flags
365
Examples
365
LDR and STR, Immediate Offset
365
Syntax
365
Operation
365
Condition Flags
366
Examples
366
LDR and STR, Register Offset
366
Syntax
366
Operation
366
Restrictions
367
Condition Flags
367
Examples
367
LDR, PC-Relative
367
Syntax
367
Operation
367
LDM and STM
367
Syntax
368
Operation
368
Restrictions
368
Condition Flags
368
Examples
369
Incorrect Examples
369
PUSH and POP
369
Syntax
369
Operation
369
NXP Semiconductors N.V. 2016. All Rights Reserved
369
Restrictions
369
Condition Flags
369
Examples
370
General Data Processing Instructions
370
ADC, ADD, RSB, SBC, and SUB
370
Syntax
370
Operation
371
Restrictions
371
Examples
372
AND, ORR, EOR, and BIC
372
Syntax
372
Operation
373
Restrictions
373
Condition Flags
373
Examples
373
ASR, LSL, LSR, and ROR
373
Syntax
373
Operation
374
Restrictions
374
Condition Flags
374
Examples
374
CMP and CMN
374
Syntax
374
Operation
375
Restrictions
375
Condition Flags
375
Examples
375
MOV and MVN
375
Syntax
375
Operation
376
Restrictions
376
Condition Flags
376
Example
376
Muls
376
Syntax
376
Operation
377
Restrictions
377
Condition Flags
377
Examples
377
REV, REV16, and REVSH
377
Syntax
377
Condition Flags
378
Examples
378
SXT and UXT
378
Syntax
378
Operation
378
Restrictions
378
Tst
378
Syntax
379
Operation
379
Restrictions
379
Condition Flags
379
Examples
379
Branch and Control Instructions
379
B, BL, BX, and BLX
379
Operation
380
Restrictions
380
Condition Flags
380
Examples
380
Miscellaneous Instructions
381
Bkpt
381
Syntax
381
Operation
382
Restrictions
382
Condition Flags
382
Examples
382
Cps
382
Syntax
382
Dmb
382
Operation
383
Restrictions
383
Condition Flags
383
Examples
383
Dsb
383
Syntax
383
Isb
383
Restrictions
384
Condition Flags
384
Examples
384
Mrs
384
Syntax
384
Operation
384
Msr
384
Operation
385
Restrictions
385
Condition Flags
385
Examples
385
Nop
385
Syntax
385
Sev
385
Restrictions
386
Condition Flags
386
Examples
386
Svc
386
Syntax
386
Operation
386
Wfe
386
Restrictions
387
Condition Flags
387
Examples
387
Wfi
387
Syntax
387
Operation
387
Examples
388
Peripherals
388
About the ARM Cortex-M0
388
Nested Vectored Interrupt Controller
388
Accessing the Cortex-M0 NVIC Registers Using CMSIS
389
Interrupt Set-Enable Register
389
Interrupt Clear-Enable Register
389
Interrupt Set-Pending Register
390
Interrupt Clear-Pending Register
390
Interrupt Priority Registers
391
Level-Sensitive and Pulse Interrupts
391
Hardware and Software Control of Interrupts 392 23.5.2.8 NVIC Usage Hints and Tips
392
NVIC Programming Hints
393
System Control Block
393
The CMSIS Mapping of the Cortex-M0 SCB Registers
393
CPUID Register
393
Interrupt Control and State Register
394
Application Interrupt and Reset Control Register
396
System Control Register
397
Configuration and Control Register
397
System Handler Priority Registers
398
System Handler Priority Register 2
398
System Handler Priority Register 3
398
SCB Usage Hints and Tips
399
System Timer, Systick
399
Systick Control and Status Register
399
Systick Reload Value Register
400
Calculating the RELOAD Value
400
Systick Current Value Register
400
Systick Calibration Value Register
400
Systick Usage Hints and Tips
401
Cortex-M0 Instruction Summary
402
Abbreviations
405
References
405
Legal Information
406
Definitions
406
Disclaimers
406
Trademarks
406
Tables
407
Figures
414
Contents
415
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