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GigaDevice Semiconductor GD32G553 User Manual

Arm cortex-m33 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32G553

®

Arm

Cortex

-M33 32-bit MCU

®

User Manual

Revision 1.0

(Nov 2024)

Table of Contents

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Summary of Contents for GigaDevice Semiconductor GD32G553

Page 1 GigaDevice Semiconductor Inc. GD32G553 ® Cortex -M33 32-bit MCU ® User Manual Revision 1.0 (Nov 2024)
Page 2: Table Of Contents
GD32G553 User Manual Table of Contents Table of Contents ......................2 List of Figures ......................25 List of Tables ........................ 35 1. System and memory architecture ................ 40 ® ® -M33 processor ..................40 1.1. Cortex System architecture ....................... 41 1.2.
Page 3 GD32G553 User Manual 1.7.24. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=14) ........84 1.7.25. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=14) ........86 1.7.26. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=14) ........87 1.8. Device electronic signature ..................89 1.8.1. Memory density information ....................89 1.8.2.
Page 4 GD32G553 User Manual 2.4.14. DCRP end address register 1(FMC_DCRP_EADDR1) ............125 2.4.15. Bank1 erase/program protection area 0 register (FMC_BK1WP0) ........126 2.4.16. Bank1 erase/program protection area 1 register (FMC_BK1WP1) ........127 2.4.17. Bank0 secure user area register (FMC_BK0SCR) ............. 127 2.4.18.
Page 5 GD32G553 User Manual 4.3.12. AHB2 enable register (RCU_AHB2EN) ................178 4.3.13. AHB3 enable register (RCU_AHB3EN) ................180 4.3.14. APB1 enable register (RCU_APB1EN) ................181 4.3.15. APB2 enable register (RCU_APB2EN) ................183 4.3.16. APB3 enable register (RCU_APB3EN) ................185 4.3.17. AHB1 sleep and deep-sleep mode enable register (RCU_AHB1SPDPEN) ...... 187 4.3.18.
Page 6 GD32G553 User Manual 6.5. Register definition......................232 6.5.1. Trigger selection for EXTOUT register 0 (TRIGSEL_EXTOUT_0) ........232 6.5.2. Trigger selection for EXTOUT register 1 (TRIGSEL_EXTOUT_1) ........232 6.5.3. Trigger selection for EXTOUT register 2 (TRIGSEL_EXTOUT_2) ........233 6.5.4. Trigger selection for EXTOUT register 3 (TRIGSEL_EXTOUT_3) ........234 6.5.5.
Page 7 GD32G553 User Manual 6.5.44. Trigger selection for CLA register 2 (TRIGSEL_CLA_2) ............ 261 6.5.45. Trigger selection for CLA register 3 (TRIGSEL_CLA_3) ............ 262 6.5.46. Trigger selection for CLA register 4 (TRIGSEL_CLA_4) ............ 262 7. General-purpose and alternate-function I/Os (GPIO and AFIO) ....... 264 7.1.
Page 8 GD32G553 User Manual 8.4.2. Peripheral handshake ......................292 8.4.3. Arbitration ..........................292 8.4.4. Address generation ......................293 8.4.5. Circular mode........................293 8.4.6. Memory to memory mode ....................293 8.4.7. Channel configuration ......................293 8.4.8. Interrupt ..........................294 8.4.9. DMA request mapping ......................295 Register definition......................
Page 9 GD32G553 User Manual 10.4.2. Free data register (CRC_FDATA) ..................322 10.4.3. Control register (CRC_CTL) ....................323 10.4.4. Initialization data register (CRC_IDATA) ................323 10.4.5. Polynomial register (CRC_POLY) ..................324 Configurable Logic Array (CLA) ..............325 11.1. Overview ........................325 11.2.
Page 10 GD32G553 User Manual 12.5.4. Health tests configure register (TRNG_HTCFG) ..............346 Cryptographic Acceleration Unit (CAU) ............348 13.1. Overview ........................348 Characteristics ......................348 13.2. CAU data type and initialization vectors ............... 349 13.3. 13.3.1. Data type ..........................349 13.3.2.
Page 11 GD32G553 User Manual Registers definition ....................393 14.5. 14.5.1. Control and status register (TMU_CS) ................393 14.5.2. Input data register (TMU_IDATA) ..................396 14.5.3. Output data register (TMU_ODATA) ................... 397 Fast Fourier Transform (FFT)................398 15.1. Overview ........................398 15.2.
Page 12 GD32G553 User Manual 16.4.3. Control register1 (DBG_CTL1) ................... 415 16.4.4. Control register2 (DBG_CTL2) ................... 417 Analog-to-digital converter (ADC) ..............419 17.1. Overview ........................419 17.2. Characteristics ......................419 Pins and internal signals ..................420 17.3. Function overview ....................421 17.4.
Page 13 GD32G553 User Manual 17.7.9. Routine sequence register 3 (ADC_RSQ3) ................ 446 17.7.10. Routine sequence register 4 (ADC_RSQ4) ................ 447 17.7.11. Routine sequence register 5 (ADC_RSQ5) ................ 448 17.7.12. Routine sequence register 6 (ADC_RSQ6) ................ 448 17.7.13. Routine sequence register 7 (ADC_RSQ7) ................ 449 17.7.14.
Page 14 GD32G553 User Manual 18.4.5. DACx_OUT0 8-bit right-aligned data holding register (DAC_OUT0_R8DH) ..... 478 18.4.6. DACx_OUT1 12-bit right-aligned data holding register (DAC_OUT1_R12DH) ....478 18.4.7. DACx_OUT1 12-bit left-aligned data holding register (DAC_OUT1_L12DH) ....478 18.4.8. DACx_OUT1 8-bit right-aligned data holding register (DAC_OUT1_R8DH) ..... 479 18.4.9.
Page 15 GD32G553 User Manual VREF ........................516 20.1. Overview ........................516 20.2. Characteristics ......................516 Function overview ....................516 20.3. 20.3.1. VREF calibration ......................... 517 Register definition ....................518 20.4. 20.4.1. Control and status register (VREF_CS) ................518 20.4.2. Calibration register (VREF_CALIB) ..................519 Watchdog timer (WDGT) ..................
Page 16 GD32G553 User Manual 22.3.18. RTC interrupts ........................545 22.4. Register definition ......................546 22.4.1. Time register (RTC_TIME) ....................546 22.4.2. Date register (RTC_DATE) ....................546 22.4.3. Control register (RTC_CTL) ....................547 22.4.4. Status register (RTC_STAT) ....................550 22.4.5. Prescaler register (RTC_PSC) ................... 552 22.4.6.
Page 17 GD32G553 User Manual 23.4. General level4 timer (TIMERx, x=15, 16) ..............839 23.4.1. Overview ..........................839 23.4.2. Characteristics ........................839 23.4.3. Block diagram ........................839 23.4.4. Function overview ....................... 840 23.4.5. Register definition (TIMERx, x=15, 16) ................858 Basic timer (TIMERx, x=5, 6) ................... 888 23.5.
Page 18 GD32G553 User Manual 24.5.8. Counter register (LPTIMER_CNT)..................930 24.5.9. External input remap register (LPTIMER_EIRMP) ............. 931 24.5.10. Input high level counter max value register (LPTIMER_INHLCMV) ........932 High-Resolution Timer (HRTIMER) ..............933 25.1. Overview ........................933 25.2. Characteristics ......................933 25.3.
Page 19 GD32G553 User Manual 27.3.5. Use DMA for data buffer access ..................1209 27.3.6. Hardware flow control ......................1211 27.3.7. Multi-processor communication ..................1212 27.3.8. LIN mode .......................... 1213 27.3.9. Synchronous mode ......................1214 27.3.10. IrDA SIR ENDEC mode ....................1215 27.3.11.
Page 20 GD32G553 User Manual 28.3.13. I2C error and interrupts ..................... 1270 28.3.14. I2C debug mode ....................... 1271 28.4. Register definition ....................1272 28.4.1. Control register 0 (I2C_CTL0) ..................1272 28.4.2. Control register 1 (I2C_CTL1) ..................1274 28.4.3. Slave address register 0 (I2C_SADDR0) ................. 1276 28.4.4.
Page 21 GD32G553 User Manual 29.5.10. CRC for classical frame register (CAN_CRCC) ............... 1339 29.5.11. Receive FIFO public filter register (CAN_RFIFOPUBF) ........... 1340 29.5.12. Receive FIFO identifier filter matching number register (CAN_RFIFOIFMN) ....1341 29.5.13. Bit timing register (CAN_BT) .................... 1341 29.5.14. Receive FIFO/mailbox private filter x register (CAN_RFIFOMPFx)(x=0..31) ....1342 29.5.15.
Page 22 GD32G553 User Manual 30.3.9. SPI interrupts ........................1372 30.4. Register definition ....................1374 30.4.1. Control register 0 (SPI_CTL0) ..................1374 30.4.2. Control register 1 (SPI_CTL1) ..................1376 30.4.3. Status register (SPI_STAT) ....................1378 30.4.4. Data register (SPI_DATA) ....................1379 30.4.5.
Page 23 GD32G553 User Manual 31.8.11. Status match register (QSPI_STATMATCH) ..............1403 31.8.12. Interval register (QSPI_INTERVAL) .................. 1404 31.8.13. Timeout register (QSPI_TMOUT) ..................1404 31.8.14. FIFO flush register (QSPI_FLUSH) .................. 1405 Clock phase delay module (CPDM) ............... 1406 32.1. Overview ........................1406 32.2.
Page 24 GD32G553 User Manual 34.3.12. Extremes monitor ......................1465 34.3.13. Data unit ..........................1465 34.3.14. HPDF interrupt ........................1467 34.4. Register definition ....................1469 34.4.1. HPDF channel x registers (x=0…7) .................. 1469 34.4.2. HPDF filter y registers (y=0…3) ..................1474 Filter arithmetic accelerator (FAC) ..............1489 35.1.
Page 25: List Of Figures
® -M33 processor ............. 41 Figure 1-1. The structure of the Cortex Figure 1-2. Series system architecture of GD32G553 series ............43 Figure 1-3. ECC decoder ........................49 Figure 2-1. Process of page erase operation .................. 98 Figure 2-2. Process of mass erase operation ................. 99 Figure 2-3.
Page 26 GD32G553 User Manual Figure 13-3. CAU diagram ........................351 Figure 13-4. DES/TDES ECB encryption ..................352 Figure 13-5. DES/TDES ECB decryption ..................353 Figure 13-6. DES/TDES CBC encryption ..................354 Figure 13-7. DES/TDES CBC decryption ..................355 Figure 13-8. AES ECB encryption ....................356 Figure 13-9.
Page 27 GD32G553 User Manual Figure 23-1. Advanced timer block diagram .................. 569 Figure 23-2. Normal mode, internal clock divided by 1 .............. 570 Figure 23-3. Counter timing diagram with prescaler division change from 1 to 2 ....571 Figure 23-4. Timing diagram of up counting mode, PSC=0 / 2 ..........572 Figure 23-5.
Page 28 GD32G553 User Manual Figure 23-43. Counter with the index signal the same as A (INDP[1:0]=2’b11) ....608 Figure 23-44. The relationship between the index signal and counter reset events ..609 Figure 23-45. The counter reset events with the FINDRST bit ..........609 Figure 23-46.
Page 29 GD32G553 User Manual Figure 23-85. Channel x output PWM duty cycle changing with CHxCOMVAL_ADD ..720 Figure 23-86. Four Channels outputs in Composite PWM mode ..........721 Figure 23-87. CHx_O output with a pulse in edge-aligned mode (CHxOMPSEL≠2’b00) ..722 Figure 23-88.
Page 30 GD32G553 User Manual Figure 23-127. Counter timing diagram with prescaler division change from 1 to 2 ..841 Figure 23-128. Timing diagram of up counting mode, PSC=0/2 ..........842 Figure 23-129. Timing diagram of up counting mode, change TIMERx_CAR on the go ... 843 Figure 23-130.
Page 31 GD32G553 User Manual Figure 25-4. Counter behavior in single pulse mode ..............937 Figure 25-5. Counter behavior in continuous mode ..............937 Figure 25-6. Repetition counter behavior in continuous mode ..........938 Figure 25-7. Repetition counter behavior in single pulse mode with CNTRSTM = 0 ..938 Figure 25-8.
Page 32 GD32G553 User Manual Figure 25-46. Regular entry for bunch mode................. 985 Figure 25-47. Delayed entry for bunch mode ................986 Figure 25-48. Emulate bunch mode example ................987 Figure 25-49. Extern event y(y=0..4) processed diagram ............989 Figure 25-50. Extern event y(y=5..9) processed diagram ............989 Figure 25-51.
Page 33 GD32G553 User Manual ................................. 1250 Figure 28-9. Data hold time ......................1251 Figure 28-10. Data setup time ......................1252 Figure 28-11. Data transmission ..................... 1254 Figure 28-12. Data reception ......................1254 Figure 28-13. I2C initialization in slave mode ................1257 Figure 28-14.
Page 34 GD32G553 User Manual Figure 33-3. Four regions of bank0 address mapping .............. 1414 Figure 33-4. Mode 1 read access ....................1420 Figure 33-5. Mode 1 write access ....................1420 Figure 33-6. Mode A read access ....................1422 Figure 33-7. Mode A write access ....................1422 Figure 33-8.
Page 35: List Of Tables
GD32G553 User Manual List of Tables Table 1-1. Bus Interconnection Matrix ....................41 Table 1-2. Memory map of GD32G553 devices ................44 Table 1-3. Boot modes ........................... 52 Table 2-1. Base address and size for 512KB-dual bank flash memory ........92 Table 2-2.
Page 36 GD32G553 User Manual Table 14-13. Mode 4 description, when IFLTEN = 1 and OFLTEN = 1 ........386 Table 14-14. Mode 4 description, when IFLTEN = 0 or OFLTEN = 0 ......... 386 Table 14-15. Mode 5 description, when IFLTEN = 1 and OFLTEN = 1 ........387 Table 14-16.
Page 37 GD32G553 User Manual Table 23-7. Output behavior of the channel in response to a BREAK0 and BREAK1 (the break input is high active) ......................599 Table 23-8. Break function input pins locked / released conditions ........601 Table 23-9. Counting direction in different quadrature decoder signals ....... 602 Table 23-10.
Page 38 GD32G553 User Manual Table 25-21. Fault channel mapping ....................992 Table 25-22. Fault channel blank ...................... 992 Table 25-23. Source of counter reset ....................993 Table 25-24. Interrupt mapping ....................... 1000 Table 25-25. DMA request mapping ....................1001 Table 27-1. Description of USART important pins ..............1205 Table 27-2.
Page 39 GD32G553 User Manual Table 33-5. NOR / PSRAM controller timing parameters ............1418 Table 33-6. EXMC_timing models ....................1419 Table 33-7. Mode 1 related registers configuration ..............1420 Table 33-8. Mode A related registers configuration ..............1422 Table 33-9. Mode 2/B related registers configuration ............... 1425 Table 33-10.
Page 40: System And Memory Architecture
GD32G553 User Manual System and memory architecture The GD32G553 series are 32-bit general-purpose microcontrollers based on the Arm ® Cortex -M33 processor. The Arm Cortex -M33 processor includes two AHB buses known as ® ® ® Code and System buses. All memory accesses of the Arm...
Page 41: System Architecture
1.2. System architecture A 32-bit multilayer bus is implemented in the GD32G553 devices, which enables parallel access paths between multiple masters and slaves in the system. The multilayer bus consists of an AHB interconnect matrix, one AHB bus and two APB buses. The interconnection relationship of the AHB interconnect matrix is shown below.
Page 42 APB1 and APB2 peripherals, the AHB2 peripherals including the APB3 peripherals and the external memories through the EXMC or the QSPI. These are interconnected using a multilayer AHB bus architecture as shown in Figure 1-2. Series system architecture of GD32G553 series below:...
Page 43: Memory Map
GD32G553 User Manual Figure 1-2. Series system architecture of GD32G553 series 12-bit ADC0~3 SAR ADC DAC0~3 3.3V POR/PDR to APB Bridge GPIO Ports A, B, C, D, E, AHB2: Fma x = 216MHz F, G QSPI QSPI_REG TPIU Decode QSPI_MEM...
Page 44: Table 1-2. Memory Map Of Gd32G553 Devices
Table 1-2. Memory map of GD32G553 devices shows the memory map of the GD32G553 devices, including Code, SRAM, peripheral, and other pre-defined regions. Almost each peripheral is allocated 1KB of space. This allows simplifying the address decoding for each peripheral.
Page 45 GD32G553 User Manual Pre-defined Address Peripherals Regions 0x4802 2800 - 0x4802 2BFF CPDM 0x4802 2400 - 0x4802 27FF Reserved 0x4802 1C00 - 0x4802 23FF Reserved 0x4802 1800 - 0x4802 1BFF TRNG 0x4802 1400 - 0x4802 17FF Reserved 0x4802 1000 - 0x4802 13FF...
Page 46 GD32G553 User Manual Pre-defined Address Peripherals Regions 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF HPDF 0x4001 6800 - 0x4001 6FFF Reserved 0x4001 5800 - 0x4001 67FF HRTIMER 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF...
Page 47 GD32G553 User Manual Pre-defined Address Peripherals Regions 0x4000 7400 - 0x4000 77FF Reserved 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF Reserved 0x4000 6000 - 0x4000 63FF...
Page 48: On-Chip Sram Memory
On-chip SRAM memory 1.3.1. The GD32G553 series contain up to 80KB of SRAM0, 16KB of SRAM1 and 32KB of TCMSRAM. It supports byte, half-word (16 bits), and word (32 bits) accesses. When reading and writing SRAM, it supports 7-bit ECC function. It can correct 1-bit error and...
Page 49: Figure 1-3. Ecc Decoder
GD32G553 User Manual It must be written before reading SRAM, otherwise it may cause ECC error. Unaligned read operations will be performed in accordance with 32-bit read operations. Non-aligned write operations will produce a read-modify-write process. For example, when 16-bit data is written...
Page 50 GD32G553 User Manual (2) The SYSCFG_CFG4 records the address where the single-bit correction error event occurred. When a single-bit correction error event is detected in TCMSRAM, EEIC: (1) The TCMSRAMECCSEIF bit int SYSCFG_STAT register will be set. Software can clear it by writing 1.
Page 51: On-Chip Flash Memory
1.4. Boot configuration The GD32G553 series provide three kinds of boot sources which can be selected by the BOOT0 pin and boot configuration bits nBOOT1, nSWBT0 and nBOOT0 in the user option byte. The details are shown in Table 1-3.
Page 52: Remap Configuration
GD32G553 User Manual Table 1-3. Boot modes Boot mode configuration Selected nBOOT1 BOOT0 nSWBT0 boot area BOOTLK nBOOT0 bit Main Flash memory Main Flash memory Main Flash memory System memory System memory Embedded SRAM0 Embedded SRAM0 After power-on sequence or a system reset, the Arm ®...
Page 53: System Configuration Controller
GD32G553 User Manual (SYSCFG_CFG0). 1.6. System configuration controller The main purposes of the system configuration controller (SYSCFG) are the following:  Remapping memory areas.  Configuring FPU interrupts.  I2C Fm+ configuration and voltage booster for I/Os anolog switches. ...
Page 54: System Configuration Registers
GD32G553 User Manual 1.7. System configuration registers SYSCFG base address: 0x4001 0000 System configuration register 0 (SYSCFG_CFG0) 1.7.1. Address offset: 0x00 Reset value: 0x0000 010X (X indicates the memory mode may be any value according to the BOOT0 pin and boot configuration bits nBOOT1, SWBT0 and nBOOT0 in the user option byte after reset) This register can be accessed by word(32-bit).
Page 55: System Configuration Register 1 (Syscfg_Cfg1)
GD32G553 User Manual System configuration register 1 (SYSCFG_CFG1) 1.7.2. Address offset: 0x04 Reset value: 0x7C00 0000 This register can be accessed by word(32-bit). I2C3FMP I2C2FMP I2C1FMP I2C0FMP PB9FMP PB8FMP PB7FMP PB6FMP Reserved IXIE IDIE OVFIE UFIE DZIE IOPIE Reserved Bits...
Page 56: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32G553 User Manual 0: Disable Fm+ mode 1: Enable Fm+ mode I2C1FMPEN I2C1 Fm+ mode enable This bit controls I2C1 Fm+ mode. 0: Disable Fm+ mode 1: Enable Fm+ mode I2C0FMPEN I2C0 Fm+ mode enable This bit controls I2C0 Fm+ mode.
Page 57: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32G553 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS[3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin 0011: PD3 pin 0100: PE3 pin 0101: PF3 pin 0110: PG3 pin...
Page 58 GD32G553 User Manual Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI7_SS[3:0] EXTI 7 sources selection 0000: PA7 pin 0001: PB7 pin 0010: PC7 pin 0011: PD7 pin...
Page 59: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32G553 User Manual EXTI sources selection register 2 (SYSCFG_EXTISS2) 1.7.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved EXTI11_SS [3:0] EXTI10_SS [3:0] EXTI9_SS [3:0] EXTI8_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 60: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32G553 User Manual 0011: PD8 pin 0100: PE8 pin 0101: PF8 pin 0110: PG8 pin EXTI sources selection register 3 (SYSCFG_EXTISS3) 1.7.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved EXTI15_SS [3:0] EXTI14_SS [3:0]...
Page 61: System Configuration Register 2 (Syscfg_Cfg2)
GD32G553 User Manual 0000: PA12 pin 0001: PB12 pin 0010: PC12 pin 0011: PD12 pin 0100: PE12 pin 0101: PF12 pin System configuration register 2 (SYSCFG_CFG2) 1.7.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by word(32-bit).
Page 62: System Status Register (Syscfg_Stat)
GD32G553 User Manual TIMER0/7/14/15/16/19 break input. 0: TCMSRAM ECC error disconnected from TIMER0/7/14/15/16/19 break input and system fault input of HRTIMER0. 1: TCMSRAM ECC error connected to TIMER0/7/14/15/16/19 break input and system fault input of HRTIMER0. SRAM1_ECC_LOCK SRAM1 ECC lock enable bit This bit is set by software and cleared by reset system only.
Page 63 GD32G553 User Manual Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved TCMSRA TCMSRA SRAM1E SRAM1E CKMNMII FLASHE SRAM0E SRAM0E Reserved MECCSE MECCME NMIPINIF CCSEIF CCMEIF CCIF CCSEIF CCMEIF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 64: System Configuration Register 3 (Syscfg_Cfg3)
GD32G553 User Manual FLASHECCIF Flash ECC NMI interrupt flag The software can clear it by writing 1. 0: no Flash ECC error 1: Flash ECC error is detected SRAM0ECCSEIF SRAM0 single bit correction interrupt flag The software can clear it by writing 1.
Page 65: System Configuration Register 4 (Syscfg_Cfg4)
GD32G553 User Manual interrupt. 0: Disable 1: Enable CKNMIIF HXTAL clock moniotor NMI interrupt enable This bit can be used to enable the HXTAL clock moniotor NMI interrupt flag connection to NMI interrupt. 0: Disable 1: Enable FLASHECCIE Flash ECC NMI interrupt flag This bit can be used to enable Flash ECC NMI interrupt flag connection to NMI interrupt.
Page 66: System Configuration Register 5 (Syscfg_Cfg5)
GD32G553 User Manual 15:10 SRAM1ECCSERRBI Which one bit has SRAM1 ECC single-bit correctable error TS[5:0] 0: no error 1: bit 0 … 32: bit 31 Reserved Must be kept at reset value. SRAM1ECCSEIF SRAM1 single bit correction error event flag This bit can be used to enable SRAM1 single bit correction event flag connection to NVIC.
Page 67: Syscfg Tcmsram Control And Status Register (Syscfg_Tcmsramcs)
GD32G553 User Manual Reserved Must be kept at reset value. TCMSRAMECCSEIE TCMSRAM single bit correction error event flag This bit can be used to enable TCMSRAM single bit correction event flag connection to NVIC. 0: Disable 1: Enable TCMSRAMECCMEIE TCMSRAM multi-bits (two bits) non-correction error event flag This bit can be used to enable TCMSRAM two bits non-correction event flag connection to NMI interrupt.
Page 68: Syscfg Tcmsram Write Protection Register (Syscfg_Tcmsramwp)
GD32G553 User Manual Reserved Reserved WP_KEY[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value WP_KEY[7:0] TCMSRAMERS write protection key Unlock write protection TCMSRAMERS SYSCFG_TCMSRAMCS register according to the following steps. Step 1. Write "0xCA” into WP_KEY[7:0] Step 2. Write "0x53” into WP_KEY[7:0] Note: Incorrect key will reactivate TCMSRAMERS write protection.
Page 69: Timer Input Selection Register 0 (Syscfg_Timercisel0)
GD32G553 User Manual Reserved CPS_RD Reserved Reserved CPS_EN Bits Fields Descriptions 31:9 Reserved Must be kept at reset value CPS_RDY Compensation cell ready flag This bit provides the status of the compensation cell. 0: I/O compensation cell not ready 1: I/O compensation cell ready Reserved Must be kept at reset value.
Page 70: Timer Input Selection Register 1 (Syscfg_Timercisel1)
GD32G553 User Manual 23:20 TIMER0_CI1_SEL[3: Selects TIMER0_CI1 input 0000: TIMER0_CH1 0001: CLA1OUT Others: Reserved 19:16 TIMER0_CI0_SEL[3: Selects TIMER0_CI0 input 0000: TIMER0_CH0 0001: CMP0 output 0010: CMP1 output 0011: CMP2 output 0100: CMP3 output 0101: CLA0OUT Others: Reserved 15:12 TIMER7_CI3_SEL[3: Selects TIMER7_CI3 input...
Page 71: Timer Input Selection Register 2 (Syscfg_Timercisel2)
GD32G553 User Manual TIMER19_CI3_SEL[3:0] TIMER19_CI2_SEL[3:0] TIMER19_CI1_SEL[3:0] TIMER19_CI0_SEL[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 TIMER19_CI3_SEL[3 Selects TIMER19_CI3 input 0000: TIMER19_CH3 0001: CLA3OUT Others: Reserved 11:8 TIMER19_CI2_SEL[3 Selects TIMER19_CI2 input 0000: TIMER19_CH2 0001: CLA2OUT Others: Reserved...
Page 72 GD32G553 User Manual 31:28 TIMER1_CI3_SEL[3: TIMER1_CI3 input selection These bits select the TIMER1_CI3 input source. 0000: TIMER1_CH3 0001: CMP0 output 0010: CMP1 output 0011: CLA3OUT Others: Reserved 27:24 TIMER1_CI2_SEL[3: TIMER1_CI2 input selection These bits select the TIMER1_CI2 input source. 0000: TIMER1_CH2...
Page 73: Timer Input Selection Register 3 (Syscfg_Timercisel3)
GD32G553 User Manual 0001: CMP2 output 0010: CLA2OUT Others: Reserved TIMER2_CI1_SEL[3: TIMER2_CI1 input selection These bits select the TIMER2_CI1 input source. 0000: TIMER2_CH1 0001: CMP0 output 0010: CMP1 output 0011: CMP2 output 0100: CMP3 output 0101: CMP4 output 0110: CMP5 output...
Page 74 GD32G553 User Manual These bits select the TIMER3_CI3 input source. 0000: TIMER3_CH3 0001: CMP5 0010: CLA3OUT Others: Reserved 27:24 TIMER3_CI2_SEL[3: TIMER3_CI2 input selection These bits select the TIMER3_CI2 input source. 0000: TIMER3_CH2 0001: CMP4 output 0010: CLA2OUT Others: Reserved 23:20...
Page 75: Timer Input Selection Register 4 (Syscfg_Timercisel4)
GD32G553 User Manual These bits select the TIMER4_CI2 input source. 0000: TIMER4_CH2 0001: CLA2OUT Others: Reserved TIMER4_CI1_SEL[3: TIMER4_CI1 input selection These bits select the TIMER4_CI1 input source. 0000: TIMER4_CH1 0001: CMP0 output 0010: CMP1 output 0011: CMP2 output 0100: CMP3 output...
Page 76 GD32G553 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 TIMER16_CI0_SEL[3 Selects TIMER16_CI0 input 0000: TIMER16_CH0 0001: CMP4 output 0010: CKOUT 0011: HXTAL/32 0100: RTC Clock 0101: LXTAL 0110: IRC40K 0111: CLA0OUT 1000: CLA1OUT 1001: CLA2OUT...
Page 77: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=0, 1, 2, 3, 4, 7, 19)
GD32G553 User Manual 0010: CMP0 output 0011: CMP1 output 0100: CMP4 output 0101: CMP6 output 0110: CLA0OUT 0111: CLA1OUT 1000: CLA2OUT 1001: CLA3OUT Others: Reserved TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=0, 1, 2, 3, 4, 1.7.21. 7, 19) Address offset: 0x100 for TIMER0...
Page 78 GD32G553 User Manual 00101: CI0 edge flag (CI0F_ED) 00110: The filtered output of channel 0 input (CI0FE0) 00111: The filtered output of channel 1 input (CI1FE1) 01000: The filtered output of external trigger input (ETIFP) 01001: Internal trigger input 4 (ITI4)
Page 79: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=0, 1, 2, 3, 4, 7, 19)
GD32G553 User Manual 00000: Restart mode disable 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3) 00101: CI0 edge flag (CI0F_ED) 00110: The filtered output of channel 0 input (CI0FE0)
Page 80 GD32G553 User Manual Address offset: 0x128 for TIMER3 Address offset: 0x134 for TIMER4 Address offset: 0x140 for TIMER7 Address offset: 0x158 for TIMER19 Reset value: 0x0000 0000 TSCFG0[4:0], TSCFG1[4:0]..TSCFG14[3:0] are mutually exclusive and cannot be configured at the same time.
Page 81 GD32G553 User Manual 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3) 00101: CI0 edge flag (CI0F_ED) 00110: The filtered output of channel 0 input (CI0FE0)
Page 82: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=0, 1, 2, 3, 4, 7, 19)
GD32G553 User Manual Others: Reserved TSCFG6[4:0] External clock mode 0 configuration The counter counts on the rising edges of the selected trigger when these bits are not 0. 00000: External clock mode 0 disable 00001: Internal trigger input 0 (ITI0)
Page 83 GD32G553 User Manual Reserved TSCFG15[4:0] Reserved TSCFG14[4:0] TSCFG13[4:0] TSCFG12[4:0] Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:16 TSCFG15[4:0] Internal trigger input source configuration 00000: Reserved 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1)
Page 84: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=14)
GD32G553 User Manual TSCFG12[4:0] Decoder mode 3 configuration 00000: disable Others: the counter will count on rising or falling edge of CI0FE0 and CI1FE1 signals. When CHxP=0, the counter will counter on the high level or the falling edge or the CIxFEx signal; When CHxP=1, the counter will counter on the low level or the rising edge or the CIxFEx signal.
Page 85 GD32G553 User Manual 10000: Reserved 10001: Reserved 10010: Reserved 10011: Internal trigger input 14 (ITI14) Others: Reserved 25:21 TSCFG4[4:0] Pause mode configuration The trigger input enables the counter clock when it is high and disables the counter when it is low when these bits are not 0.
Page 86: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=14)
GD32G553 User Manual 01011: Internal trigger input 6 (ITI6) 01100: Internal trigger input 7 (ITI7) 01101: Internal trigger input 8 (ITI8) 01110: Internal trigger input 9 (ITI9) 01111: Internal trigger input 10 (ITI10) 10000: Reserved 10001: Reserved 10010: Reserved 10011: Internal trigger input 14 (ITI14)
Page 87: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=14)
GD32G553 User Manual 01010: Internal trigger input 5 (ITI5) 01011: Internal trigger input 6 (ITI6) 01100: Internal trigger input 7 (ITI7) 01101: Internal trigger input 8 (ITI8) 01110: Internal trigger input 9 (ITI9) 01111: Internal trigger input 10 (ITI10) 10000: Reserved...
Page 88 GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved TSCFG15[4:0] Reserved Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:16 TSCFG15[4:0] Internal trigger input source configuration 00000: Reserved 00001: Internal trigger input 0 (ITI0)
Page 89: Device Electronic Signature
GD32G553 User Manual 1.8. Device electronic signature The device electronic signature contains memory density information and the 96-bit unique device ID. It is stored in the information block of the Flash memory. The 96-bit unique device ID is unique for any device. It can be used as serial numbers, or part of security keys, etc.
Page 90 GD32G553 User Manual 31:0 UNIQUE_ID[31:0] Unique device ID Base address: 0x1FFF B3EC The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF B3F0 The value is factory programmed and can never be altered by user.
Page 91: Flash Memory Controller (Fmc)
GD32G553 User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 512K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 92: Function Overview
GD32G553 User Manual 2.3. Function overview Flash memory architecture 2.3.1. The flash memory for dual bank consists of up to 512 KB main flash, which is organized into 2 X 256 pages with 1KB capacity, 2 X 13 KB information block for the boot loader. Each page of main flash memory can be erased individually.
Page 93: Error Checking And Correcting (Ecc)
GD32G553 User Manual Table 2-2. Base address and size for 512KB-single bank flash memory Block Name Address size(bytes) Page 0 0x0800 0000 - 0x0800 07FF Page 1 0x0800 0800 - 0x0800 0FFF Page 2 0x0800 1000 - 0x0800 17FF Main flash block...
Page 94: Read Operations
GD32G553 User Manual Note: If the bank is swapped, the ECC address will be reported according to the swapped address. For example, if access address 0x08000000 and in fact bank1 will be accessed, the ecc reports an error, and the error address stored is the address 0x08040000 accessed by user.
Page 95: Table 2-3. The Relation Between Wscnt And Ahb Clock Frequency When Ldo Is 1.1V
GD32G553 User Manual Table 2-3. The relation between WSCNT and AHB clock frequency when LDO is 1.1V AHB clock frequency WSCNT configured <= 10MHz 0 (0 wait state added) <= 20MHz 1 (1 wait state added) <= 50MHz 2 (2 wait state added) <= 70MHz...
Page 96: Dual Bank Architecture With Read-While-Write (Rww) Capability
GD32G553 User Manual ICODE cache Instruction cache is enabled by set the ICEN bit in the FMC_WS register. The cache has 2K bytes, and it is organized by 64 cache lines. Each cache line has 4 x 64 bits or 2 x 128 bits.
Page 97: Page Erase
GD32G553 User Manual FMC_OBKEY register. The unlocking sequence includes two write operations, which are orderly writing 0x0819 2A3B and 0x4C5D 6E7F to FMC_OBKEY register, then hardware reset the OBLK bit in FMC_CTL register to 0. The software can set OBLK bit to 1 to protect the FMC_OBCTL register, OBRLD bit and OBSTART bit in FMC_CTL register again.
Page 98: Mass Erase
GD32G553 User Manual Figure 2-1. Process of page erase operation Start Unlock the Is the LK bit 0 FMC_CTL Is the BUSY bit 0 Is the DBS bit 1 Set the PER bit, write Set the PER bit, write the PNSEL bits and...
Page 99: Main Flash Programming
GD32G553 User Manual register.  Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT register.  Read and verify the flash memory if required using a DBUS access. When the operation is executed successfully, the END in FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set.
Page 100 GD32G553 User Manual  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 101: Otp Programming
GD32G553 User Manual Figure 2-3. Process of double-word program operation Start Unlock the Is the LK bit 0 FMC_CTL Is the BUSY bit 0 Set the PG bit Perform a double-word write by CBUS Is the BUSY bit 0 Finish Note: Reading the flash should be avoided when a program / erase operation is ongoing in the same bank.
Page 102: Option Bytes
GD32G553 User Manual little probability of corrupting the data stored in flash memory. Option bytes 2.3.10. Option bytes description The option bytes registers are reloaded to relevant block of flash memory after each system reset or OBRLD bit set in FMC_CTL register, and the option bytes work. The option complement bytes are the opposite of option bytes.
Page 103 GD32G553 User Manual Address Name Description This bit can only be written when DCRP0/1 is disabled. [5]: reserved [4]: BB 0: Boot from bank0, when configured boot from main memory 1: Boot from bank1 or bank0 if bank1 is void, (or Bootloader...
Page 104 GD32G553 User Manual Address Name Description 0x1fff 7808 DCRP_SADDR0[7:0] DCRP area start address for bank0 [7]: reserved 0x1fff 7809 DCRP_SADDR0[14:8] [6:0]: DCRP area start address for bank0 0x1fff 780c DCRP_SADDR0_N[7:0] DCRP_SADDR0 complement value bit 7 to 0 DCRP_SADDR0_N[14: [7]: reserved...
Page 105 GD32G553 User Manual Address Name Description BK0WP1_EADDR[7:0] contains the last page of WP second area in bank0. DBS=0 BK0WP1_EADDR[7:0] contains the last page of WP second area for all memory BK0WP1_SADDR_N[7: 0x1fff 7824 BK0WP1_SADDR complement value bit 7 to 0...
Page 106 GD32G553 User Manual Address Name Description BK1WP0_EADDR[7:0] contains the last page of WP third area for all memory BK1WP0_SADDR_N[7: 0x1fff f81c BK1WP0_SADDR complement value bit 7 to 0 BK1WP0_EADDR_N[7: 0x1fff f81e BK1WP0_EADDR complement value bit 7 to 0 DBS=1 BK1WP1_SADDR[7:0] contains the first page of WP second area in bank1.
Page 107: Dedicated Code Read Protection Area (Dcrp)
GD32G553 User Manual  Wait until all the operations have been finished by checking the value of the BUSY bit in the FMC_STAT register. Launch a system power on / down reset (or exit from Standby mode) or set the ...
Page 108: Erase/Program Protection (Wp)
GD32G553 User Manual The DCRP area are defined by a start address offset and an end address offset. If single bank mode is selected, the minimum DCRP area is 32 bytes. The DCRP areax (x= 0,1) is defined  From bank base address + [FMC_DCRP_SADDRx x 16] (include) to the address: bank base address + [(FMC_DCRP_EADDRx + 1) x 16] (exclude).
Page 109: Security Protection (Spc)
GD32G553 User Manual are defined by a start address offset and an end address offset. The page protection function can be individually enabled by configuring the WP address registers: FMC_BK0WPx (x = 0,1) and FMC_BK1WPx (x = 0,1). If single bank mode is selected (DBS = 0), four WP areas can be defined in the bank with a granularity of 2 Kbytes.
Page 110: Secure User Area (Scr)
GD32G553 User Manual No protection: when setting SPC byte and its complement value to 0xAA55, no protection performed. The main flash and option bytes block are accessible by all operations. Low level protection: when setting SPC byte value to any value except 0xAA or 0xCC, the low security protection is performed.
Page 111: Disabling Core Debug Access
GD32G553 User Manual address(included) to bank1 base address + [(SCR_PAGE_CNT1[8:0]) x 0x400] (excluded). Disabling core debug access 2.3.15. The debug access to the core can be disabled temporarily when executing sensitive code or accessing sensitive data in securable user area.
Page 112: Register Definition
GD32G553 User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0004 0600 This register has to be accessed by word (32-bit) access. Reserved DBGEN Reserved SLP_MDS RUN_MD Reserved DCRST...
Page 113: Unlock Flash Mode During Run Mode Key Register (Fmc_Runkey)
GD32G553 User Manual ICRST Instruction cache reset. This bit can be write only when ICEN is set to 0. 0: No effect 1: Instruction cache reset DCEN Data cache enable 0: Data cache disable 1: Data cache enable ICEN Instruction cache enable...
Page 114: Unlock Key Register (Fmc_Key)
GD32G553 User Manual RUN_KEY2: 0xFAFBFCFD Unlock key register (FMC_KEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock register These bits can only be written by software.
Page 115 GD32G553 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved BUSY OBERR RPERR Reserved PGSERR PGMERR PGAERR WPERR PGERR Reserved OPRERR ENDF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields...
Page 116: Control Register (Fmc_Ctl)
GD32G553 User Manual When an erase/program protection error occurs, this bit is set by hardware. The software can clear it by writing 1. 0: No write protection error occurs 1: Write protection error occurs PGERR Program error flag bit When programming to the flash while it is not 0xFFFF FFFF FFFF FFFF, this bit is set by hardware.
Page 117 GD32G553 User Manual exiting the secure user area, and can only be written once. In case DBS=0, this bit is useless. 0: Disable secure user area for bank1 1: Enable secure user area for bank1 SCR0 Bank0 secure user area enable bit.
Page 118: Ecc Control And Status Register (Fmc_Ecccs)
GD32G553 User Manual This bit is set or cleared by software. 0: No effect 1: Main flash mass erase command for bank1 14:13 Reserved Must be kept at reset value BKSEL Bank number selection for page erase. DBS=1 0: Bank0 is selected for page erase.
Page 119 GD32G553 User Manual ECCADDR[15:0] Bits Fields Descriptions ECCDET0 Two bit errors detected flag. When DBS = 0: This bit set when two ECC errors have been detected in LSB bits (bits 63:0). The software can clear it by writing 1.
Page 120: Option Byte Control Register (Fmc_Obctl)
GD32G553 User Manual ECCCORIE One-bit error correction interrupt enable. 0: Disable one-bit error correction interrupt. 1: Enable one-bit error correction interrupt. This bit enables the interrupt generation when the ECCCOR bit is set. Reserved Must be kept at reset value...
Page 121 GD32G553 User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:28 NRST_MDSEL[1:0] NRST pin mode selection. 00: NRST pin configure as input/output mode. 01: A low level on the NRST pin can reset system, internal reset cannot drive NRST pin.
Page 122: Dcrp Start Address Register 0(Fmc_Dcrp_Saddr0)
GD32G553 User Manual 0: FWDGT is suspend in system standby mode 1: FWDGT is running in system standby mode FWDGSPD_DPSLP FWDGT suspend option in deepsleep mode configuration bit 0: FWDGT is suspend in system deepsleep mode 1: FWDGT is running in system deepsleep mode.
Page 123: Dcrp End Address Register 0(Fmc_Dcrp_Eaddr0)
GD32G553 User Manual This register has to be accessed by word(32-bit). Reserved Reserved DCRP0_SADDR [14:0] Bits Fields Descriptions 31:15 Reserved Must be kept at reset value 14:0 DCRP0_SADDR [14:0] DCRP area start address offset configuration bits for bank0 DBS=1: DCRP0_SADDR contains the start address of the bank0 DCRP area.
Page 124: Bank0 Erase/Program Protection Area 0 Register (Fmc_Bk0Wp0)
GD32G553 User Manual Bank0 erase/program protection area 0 register (FMC_BK0WP0) 2.4.11. Address offset: 0x2C Reset value: 0xFEXX FEXX This register has to be accessed by word (32-bit). Reserved BK0WP0_EADDR[7:0] Reserved BK0WP0_SADDR[7:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value...
Page 125: Dcrp Start Address Register 1(Fmc_Dcrp_Saddr1)
GD32G553 User Manual 31:24 Reserved Must be kept at reset value WP second area end offset 23:16 BK0WP1_EADDR[7:0 DBS=1: BK0WP1_EADDR[7:0] contains the last page of the WP second area for bank0. DBS=0: BK0WP1_EADDR[7:0] contains the last page of the WP second area for all memory.
Page 126: Bank1 Erase/Program Protection Area 0 Register (Fmc_Bk1Wp0)
GD32G553 User Manual Reserved DCRP1_EAREA [14:0] Bits Fields Descriptions 31:15 Reserved Must be kept at reset value 14:0 DCRP1_EADDR DCRP area end address offset configuration bits for bank1 [14:0] DBS=1: DCRP1_EADDR contains the end address of the bank1 DCRP area.
Page 127: Bank1 Erase/Program Protection Area 1 Register (Fmc_Bk1Wp1)
GD32G553 User Manual Bank1 erase/program protection area 1 register (FMC_BK1WP1) 2.4.16. Address offset: 0x50 Reset value: 0xFEXX FEXX This register has to be accessed by word (32-bit). Reserved BK1WP1_EADDR[7:0] Reserved BK1WP1_SADDR[7:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value...
Page 128: Bank1 Secure User Area Register (Fmc_Bk1Scr)
GD32G553 User Manual This bit is set to force boot from user flash area. BOOTLK 0: Support flash, RAM and system boot 1: Only boot from main flash 15:9 Reserved Must be kept at reset value SCR_PAGE_CNT0[8: Configure the number of pages in the bank0 secure user area.
Page 129 GD32G553 User Manual Bits Field Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by software. These bits are unchanged constant after power on. These bits are one time program when the chip produced.
Page 130: Power Management Unit (Pmu)
GD32G553 User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices series. The Power management unit (PMU), provides three types of power GD32G553 saving modes, including Sleep, Deep-sleep, and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 131: Function Overview
GD32G553 User Manual 3.3. Function overview provides details on the internal configuration of the PMU Figure 3-1. Power supply overview and the relevant power domains. Figure 3-1. Power supply overview Backup Domain LXTAL BPOR Power Switch 3.3V BREG Domain WKUPR...
Page 132 GD32G553 User Manual mode until V is completely powered up. Also the application software can trigger the Backup domain software reset by setting the BKPRST bit in the RCU_BDCTL register to reset the Backup domain. The clock source of the Real Time Clock (RTC) circuit can be derived from the Internal 32KHz RC oscillator (IRC32K) or the Low Speed Crystal oscillator (LXTAL), or HXTAL clock divided by 32.
Page 133: Figure 3-2. Waveform Of The Backup Domain Voltage Thresholds
GD32G553 User Manual Figure 3-2. Waveform of the Backup domain voltage thresholds BAKT BAKB VBATHF VBATLF Temperature voltage thresholds The junction temperature can be monitored by comparing it with two threshold levels, TEMP high and TEMP low. TEMPHF and TEMPLF flags, in the PMU_CTL1, indicate whether the device temperature is higher or lower than the threshold.
Page 134: Vdd / Vdda Power Domain
GD32G553 User Manual Figure 3-3. Temperature thresholds Temperature TEMP high TEMP low TEMPHF TEMPLF VDD / VDDA power domain 3.3.2. domain includes two parts: V domain and V domain. V domain includes HXTAL (High Speed Crystal oscillator), IRC8M (Internal 8MHz RC oscillator), IRC32K (Internal 32KHz RC oscillator), LDO (Voltage Regulator), POR/PDR (Power On/Down Reset), FWDGT (Free Watchdog Timer), all pads except PC13/PC14/PC15, etc.
Page 135: Figure 3-5. Waveform Of The Bor
GD32G553 User Manual Figure 3-4. Waveform of the POR/PDR hyst RSTTEMPO Power Reset (Active Low)  The BOR circuit is used to detect V and generate the power reset signal which resets the whole chip except the Backup domain when the BOR_TH bits in option bytes is not 0b11 and the supply voltage is lower than the specified threshold which defined in the BOR_TH bits in option bytes.
Page 136: Figure 3-6. Waveform Of The Lvd Threshold
GD32G553 User Manual domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in PMU_CS, indicates if V higher or lower than the LVD threshold.
Page 137: Power Domain
GD32G553 User Manual Figure 3-7. Waveform of the VAVD threshold VAVD threshold hyst VAVDF Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply V is implemented to achieve better performance of analog circuits.
Page 138: Figure 3-8. Waveform Of Vovd
GD32G553 User Manual 1.1V voltage thresholds detector There is an internal 1.1V power over voltage detector, when VOVDEN is 0b1, it means 1.1V power over voltage detector is enabled. Once V1.1V power domain is over than a programmed threshold selected by the VOVDVC[1:0] bits in the power control register(PMU_CTL0), VOVDF0 will be set immediately after two flip-flops synchronization of the analog output.
Page 139: Power Saving Modes
Power saving modes 3.3.4. After a system reset or a power reset, the GD32G553 MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, PCLK2, PCLK3) or gating the clocks of the unused peripherals.
Page 140 GD32G553 User Manual Mode Sleep Deep-sleep Standby Any interrupt for Any interrupt from EXTI NRST pin lines for WFI WKUP pins Any event (or Wakeup Any event(or interrupt FWDGT reset interrupt when when SEVONPEND is 1) SEVONPEND is 1) from EXTI for WFE...
Page 141: Standby Mode
GD32G553 User Manual in low power mode. Note: In order to enter Deep-sleep mode smoothly, all EXTI line pending status (in the EXTI_PD register) and related peripheral flags must be reset. If not, the program will skip the entry process of Deep-sleep mode to continue to execute the following procedure.
Page 142: Register Definition
GD32G553 User Manual 3.4. Register definition PMU base address: 0x40007000 Control register 0 (PMU_CTL0) 3.4.1. Address offset: 0x00 Reset value: 0x0002 6000 This register can be accessed by word(32-bit) Reserved VUVDVC VOVDVC VUVDEN VOVDEN Reserved VAVDVC VAVDEN DSLPVS LDOVS[4:0] Reserved...
Page 143 GD32G553 User Manual 01: Configure V analog voltage detector voltage level to 2.2V 10: Configure V analog voltage detector voltage level to 2.6V 11: Configure V analog voltage detector voltage level to 2.9V VAVDEN analog voltage detector voltage enable bit This bit is set and cleared by software.
Page 144: Control And Status Register 0 (Pmu_Cs)
GD32G553 User Manual 101: 2.9V 110: 3.0V 111: PA10 input analog voltage LVD_IN (compared with 1.2V) LVDEN Low Voltage Detector Enable 0: Disable Low Voltage Detector 1: Enable Low Voltage Detector STBRST Standby Flag Reset 0: No effect 1: Reset the standby flag This bit is always read as 0.
Page 145 GD32G553 User Manual WKUP pin4 wakes up the system from the power saving mode. As the WKUP pin4 is active high, the WKUP pin4 is internally configured to input pull down mode. And set this bit will trigger a wakeup event when the input is already high.
Page 146: Control Register 1 (Pmu_Ctl1)
GD32G553 User Manual this bit is set and cleared by hardware. It si valid only if VUVDEN is enabled. 0: V v is higher than VUVD threshold(0.6V). 1: V v is equal or lower than VUVD threshold(0.6V). VOVDF0 v over voltage detector flag bit.
Page 147: Control Register 2 (Pmu_Ctl2)
GD32G553 User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TEMPHF Temperature level monitoring versus high threshold 0: Temperature below high threshold level. 1: Temperature equal or above high threshold level. TEMPLF Temperature level monitoring versus low threshold 0: Temperature above low threshold level.
Page 148: Control Register 3(Pmu_Ctl3)
GD32G553 User Manual Reserved VCRSEL VCEN Reserved Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. VCRSEL VBAT battery charging resistor selection 0: 5 kOhms resistor is selected for charing VBAT battery. 1:1.5 kOhms resistor is selected for charing VBAT battery.
Page 149 GD32G553 User Manual 1: Digital filter is enabled and filter spikes with a length of up to 1024 * T PCLK 255: Digital filter is enabled and filter spikes with a length of up to 255*1024 * T PCLK...
Page 150: Reset And Clock Unit (Rcu)
Overview 4.1.1. GD32G553 reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain. The system reset resets the processor core and peripheral IP components except for the SW-DP controller and the backup domain.
Page 151: Figure 4-1. The System Reset Circuit
GD32G553 User Manual Input/output mode (default mode): the GPIO function of the NRST pin is not available in this mode. The reset signal can be transferred from the NRST pin to the device, causing the device to reset, the reset pulse signal can be reflected through the NRST pin, and the minimum reset pulse duration is 20 μs.
Page 152: Figure 4-2. Clock Tree
GD32G553 User Manual which can source from the IRC8M, HXTAL or PLL. The maximum operating frequency of the system clock (CK_SYS) can be up to 216 MHz. Figure 4-2. Clock tree HCLK AHB enable to AHB bus, Cortex-M33, SRAM, DMA, peripherals SCS[1:0] ÷...
Page 153 GD32G553 User Manual The CANx (x=0, 1, 2) is clocked by HXTAL clock or PLLQ or APB2 clock, which selected by CANxSEL (x=0, 1, 2) bits in configuration register 1 (RCU_CFG1). The HPDF_AUDIO is clocked by the clock of CK_PLLQ or CK_IRC8M or External HPDF_CKIN PIN which defined by HPDFAUDIOSEL bits in RCU_CFG1 register.
Page 154: Characteristics
GD32G553 User Manual Characteristics 4.2.2.  4 to 48 MHz high speed crystal oscillator (HXTAL).  Internal 8 MHz RC oscillator (IRC8M).  32,768 Hz low speed crystal oscillator (LXTAL).  Internal 32KHz RC oscillator (IRC32K).  PLL clock source can be HXTAL, IRC8M.
Page 155: Figure 4-4. Hxtal Clock Source In Bypass Mode
GD32G553 User Manual Figure 4-4. HXTAL clock source in bypass mode OSCIN OSCOUT Exte rnal cl ock Internal 8M RC oscillators (IRC8M) The internal 8M RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up.
Page 156: System Clock (Ck_Sys) Selection
GD32G553 User Manual Low speed crystal oscillator (LXTAL) The low speed external crystal or ceramic resonator oscillator, which has a frequency of 32,768 Hz, produces a low power but highly accurate clock source for the real time clock circuit. The LXTAL oscillator can be switched on or off using the LXTALEN bit in the backup domain control register (RCU_BDCTL).
Page 157: Clock Output Capability
GD32G553 User Manual LXTAL clock monitor (LCKM) A clock monitor on LXTAL can be activated by software writing the LCKMEN, in the control register, RCU_CTL. LCKMEN can not be enabled before LXTAL and IRC32K are enabled and ready. A 4-bits plus one counter will work at IRC32K domain when LCKMEN enable. If the LXTAL clock has stuck at 0 / 1 error or slow down about 20KHz, the counter will overflow.
Page 158 GD32G553 User Manual...
Page 159: Register Definition
GD32G553 User Manual Register definition 4.3. RCU base address: 0x4002 1000 Control register (RCU_CTL) 4.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALST HXTALB HXTALST HXTALE...
Page 160: Pll Register (Rcu_Pll)
GD32G553 User Manual power on reset or clearing CKMIF by software. Note: When the HXTAL clock monitor is enabled, the hardware will automatically enable the IRC8M internal RC oscillator regardless of the control bit, IRC8MEN, state. HXTALBPS High speed crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0.
Page 161 GD32G553 User Manual Reset value: 0x0000 0400 To configure the PLL clock, refer to the following formula: CK_PLLVCOSRC = CK_PLLSRC / PLLPSC CK_PLLVCO = CK_PLLVCOSRC × PLLN CK_PLLP = CK_PLLVCO / PLLP CK_PLLQ = CK_PLLVCO / PLLQ CK_PLLR = CK_PLLVCO / PLLR This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 162 GD32G553 User Manual 0: IRC8M clock selected as source clock of PLL 1: HXTAL selected as source clock of PLL PLLREN PLLR divider output enable This bit is set and reset by software. The PLLREN bit can be written only if the PLLEN is 0.
Page 163: Clock Configuration Register 0 (Rcu_Cfg0)
GD32G553 User Manual 0001010: PLLN = 10 … 10110100: PLLN = 180 Reserved Must be kept at reset value. PLLPSC[3:0] The PLL VCO source clock prescaler Set and reset by software when the PLL is disable. These bits used to generate the clock of PLL VCO source clock (CK_PLLVCOSRC) from PLL source clock (CK_PLLSRC) which described in PLLSEL in RCU_PLL register.
Page 164 GD32G553 User Manual 010: The CK_OUT is divided by 4 011: The CK_OUT is divided by 8 100: The CK_OUT is divided by 16 Others: Reserved 23:21 CKOUTSEL[2:0] CK_OUT clock source selection Set and reset by software. 000: No clock selected...
Page 165: Clock Interrupt Register (Rcu_Int)
GD32G553 User Manual 1111: (CK_SYS / 512) selected SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock. 00: Select CK_IRC8M as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source...
Page 166 GD32G553 User Manual 0: LXTAL clock operating normally 1: LXTAL clock stuck 26:24 Reserved Must be kept at reset value. CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag. 0: Not reset CKMIF flag...
Page 167 GD32G553 User Manual Set and reset by software to enable/disable the IRC8M stabilization interrupt 0: Disable the IRC8M stabilization interrupt 1: Enable the IRC8M stabilization interrupt LXTALSTBIE LXTAL stabilization interrupt enable Set and reset by software to enable/disable LXTAL stabilization interrupt...
Page 168: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32G553 User Manual 1: LXTAL stabilization interrupt generated IRC32KSTBIF IRC32K stabilization interrupt flag Set by hardware when the Internal 32kHz RC oscillator clock is stable and the IRC32KSTBIE bit is set. Reset when setting the IRC32KSTBIC bit by software. 0: No IRC32K stabilization clock ready interrupt generated...
Page 169: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32G553 User Manual 20:16 Reserved Must be kept at reset value. CLARST CLA reset This bit is set and reset by software. 0: No reset 1: Reset the CLA 14:13 Reserved Must be kept at reset value. CRCRST CRC reset This bit is set and reset by software.
Page 170 GD32G553 User Manual PDRST GPIO port D reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port D PCRST GPIO port C reset This bit is set and reset by software. 0: No reset...
Page 171: Ahb3 Reset Register (Rcu_Ahb3Rst)
GD32G553 User Manual AHB3 reset register (RCU_AHB3RST) 4.3.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved EXMCRS Reserved QSPIRST Bits Fields Descriptions 31:2 Reserved Must be kept at reset value.
Page 172 GD32G553 User Manual This bit is set and reset by software. 0: No reset 1: Reset power control unit 27:25 Reserved Must be kept at reset value. I2C3RST I2C3 reset This bit is set and reset by software. 0: No reset...
Page 173 GD32G553 User Manual This bit is set and reset by software. 0: No reset 1: Reset the SPI2 SPI1RST SPI1 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI1 13:12 Reserved Must be kept at reset value.
Page 174: Apb2 Reset Register (Rcu_Apb2Rst)
GD32G553 User Manual TIMER1RST TIMER1 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER1 APB2 reset register (RCU_APB2RST) 4.3.9. Address offset: 0x24 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 175 GD32G553 User Manual 0: No reset 1: Reset the TIMER15 TIMER14RST TIMER14 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER14 TIMER19RST TIMER19 reset This bit is set and reset by software. 0: No reset...
Page 176: Apb3 Reset Register (Rcu_Apb3Rst)
GD32G553 User Manual This bit is set and reset by software. 0: No reset 1: Reset the CMP VREFRST VREF reset This bit is set and reset by software. 0: No reset 1: Reset the VREF TIMER7RST TIMER7 reset This bit is set and reset by software.
Page 177: Ahb1 Enable Register (Rcu_Ahb1En)
GD32G553 User Manual DAC1RST DAC1 reset This bit is set and reset by software. 0: No reset 1: Reset DAC1 DAC0RST DAC0 reset This bit is set and reset by software. 0: No reset 1: Reset DAC0 DACHOLDRST DAC hold clock reset This bit is set and reset by software.
Page 178: Ahb2 Enable Register (Rcu_Ahb2En)
GD32G553 User Manual CLAEN Reserved CRCEN Reserved Bits Fields Descriptions FFTEN FFT clock enable This bit is set and reset by software. 0: Disabled FFT clock 1: Enabled FFT clock 30:24 Reserved Must be kept at reset value. DMAMUXEN DMAMUX clock enable This bit is set and reset by software.
Page 179 GD32G553 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved PGEN PFEN PEEN PDEN PCEN PBEN PAEN Reserved Reserved TMUEN TRNGEN Reserved CAUEN Reserved FACEN Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value.
Page 180: Ahb3 Enable Register (Rcu_Ahb3En)
GD32G553 User Manual TMUEN TMU clock enable This bit is set and reset by software. 0: Disabled TMU clock 1: Enabled TMU clock TRNGEN TRNG clock enable This bit is set and reset by software. 0: Disabled TRNG clock 1: Enabled TRNG clock Reserved Must be kept at reset value.
Page 181: Apb1 Enable Register (Rcu_Apb1En)
GD32G553 User Manual 0: Disabled EXMC clock 1: Enabled EXMC clock APB1 enable register (RCU_APB1EN) 4.3.14. Address offset: 0x40 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). UART4E UART3E USART2 USART1 Reserved PMUEN Reserved...
Page 182 GD32G553 User Manual 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software. 0: Disabled UART3 clock...
Page 183: Apb2 Enable Register (Rcu_Apb2En)
GD32G553 User Manual TIMER6EN TIMER6 clock enable This bit is set and reset by software. 0: Disabled TIMER6 clock 1: Enabled TIMER6 clock TIMER5EN TIMER5 clock enable This bit is set and reset by software. 0: Disabled TIMER5 clock 1: Enabled TIMER5 clock...
Page 184 GD32G553 User Manual TRIGSELEN TRIGSEL clock enable This bit is set and reset by software. 0: Disabled TRIGSEL clock 1: Enabled TRIGSEL clock Reserved Must be kept at reset value. HRTIMEREN HRTIMER clock enable This bit is set and reset by software.
Page 185: Apb3 Enable Register (Rcu_Apb3En)
GD32G553 User Manual 1: Enabled SPI0 clock Reserved Must be kept at reset value. CAN2EN CAN2 clock enable This bit is set and reset by software. 0: Disabled CAN2 clock 1: Enabled CAN2 clock CAN1EN CAN1 clock enable This bit is set and reset by software.
Page 186 GD32G553 User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). DACHOL Reserved DAC3EN DAC2EN DAC1EN DAC0EN Reserved ADC3EN ADC2EN ADC1EN ADC0EN Reserved Bits Fields Descriptions 31:21 Reserved Must be kept at reset value.
Page 187: Ahb1 Sleep And Deep-Sleep Mode Enable Register (Rcu_Ahb1Spdpen)
GD32G553 User Manual 0: Disabled ADC2 clock 1: Enabled ADC2 clock ADC1EN ADC1 clock enable This bit is set and reset by software. 0: Disabled ADC1 clock 1: Enabled ADC1 clock ADC0EN ADC0 clock enable This bit is set and reset by software.
Page 188: Ahb2 Sleep And Deep-Sleep Mode Enable Register (Rcu_Ahb2Spdpen)
GD32G553 User Manual 1: Enabled DMA1 clock when sleep and deep sleep mode DMA0SPDPEN DMA0 clock enable when sleep and deep sleep mode This bit is set and reset by software. 0: Disabled DMA0 clock when sleep and deep sleep mode...
Page 189 GD32G553 User Manual Reset value: 0x00FE 00CA This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PGSPDP PFSPDP PESPDP PDSPDP PCSPDP PBSPDP PASPDP Reserved Reserved TMUSPD TRNGSP CAUSPD FACSPD Reserved Reserved Reserved Reserved DPEN Bits Fields Descriptions 31:24 Reserved Must be kept at reset value.
Page 190: Ahb3 Sleep And Deep-Sleep Mode Enable Register (Rcu_Ahb3Spdpen)
GD32G553 User Manual 0: Disabled GPIO port A clock when sleep and deep sleep mode 1: Enabled GPIO port A clock when sleep and deep sleep mode 16:8 Reserved Must be kept at reset value. TMUSPDPEN TMU clock enable when sleep and deep sleep mode This bit is set and reset by software.
Page 191: Apb1 Sleep And Deep-Sleep Mode Enable Register (Rcu_Apb1Spdpen)
GD32G553 User Manual QSPISPDPEN QSPI clock enable when sleep and deep sleep mode This bit is set and reset by software. 0: Disabled QSPI clock when sleep and deep sleep mode 1: Enabled QSPI clock when sleep and deep sleep mode...
Page 192 GD32G553 User Manual 0: Disabled I2C1 clock when sleep and deep sleep mode 1: Enabled I2C1 clock when sleep and deep sleep mode I2C0SPDPEN I2C0 clock enable when sleep and deep sleep mode This bit is set and reset by software.
Page 193: Apb2 Sleep And Deep-Sleep Mode Enable Register (Rcu_Apb2Spdpen)
GD32G553 User Manual This bit is set and reset by software. 0: Disabled LPTIMER clock when sleep and deep sleep mode 1: Enabled LPTIMER clock when sleep and deep sleep mode Reserved Must be kept at reset value. TIMER6SPDPEN TIMER6 clock enable when sleep and deep sleep mode This bit is set and reset by software.
Page 194 GD32G553 User Manual TIMER19 SYSCFG SPI0SPD CAN2SP CAN1SP CAN0SP USART0 CMPSPD VREFSP TIMER7S TIMER0S Reserved Reserved Reserved SPDPEN SPDPEN DPEN DPEN DPEN SPDPEN DPEN PDPEN PDPEN Bits Fields Descriptions TRIGSELSPDPEN TRIGSEL clock enable when sleep mode This bit is set and reset by software.
Page 195 GD32G553 User Manual 1: Enabled SYSCFG clock when sleep and deep sleep mode Reserved Must be kept at reset value. SPI0SPDPEN SPI0 clock enable when sleep and deep sleep mode This bit is set and reset by software. 0: Disabled SPI0 clock when sleep and deep sleep mode...
Page 196: Apb3 Sleep And Deep-Sleep Mode Enable Register (Rcu_Apb3Spdpen)
GD32G553 User Manual 0: Disabled TIMER0 clock when sleep and deep sleep mode 1: Enabled TIMER0 clock when sleep and deep sleep mode APB3 sleep and deep-sleep mode enable register (RCU_APB3SPDPEN) 4.3.22. Address offset: 0x68 Reset value: 0x001F 0F00 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 197: Backup Domain Control Register (Rcu_Bdctl)
GD32G553 User Manual 15:12 Reserved Must be kept at reset value. ADC3SPDPEN ADC3 clock enable when sleep and deep sleep mode This bit is set and reset by software. 0: Disabled ADC3 clock when sleep and deep sleep mode 1: Enabled ADC3 clock when sleep and deep sleep mode...
Page 198 GD32G553 User Manual LSCKOUTSEL Low speed clock output selection 0: IRC32K selected 1: LXTAL selected LSCKOUTEN Low speed clock output enalbe 0: Low speed clock output(LSCKOUT) disable 1: Low speed clock output(LSCKOUT) enable 23:17 Reserved Must be kept at reset value.
Page 199: Reset Source/Clock Register (Rcu_Rstsck)
GD32G553 User Manual LCKMEN should be enabled only on the LXTAL is enabled (LXTALEN bit enabled) and ready (LXTALSTB flag set by hardware). Note:Once LCKMEN bit is set, this bit can be reset by system reset or reseting this bit after detecting LXTAL clock failure (LCKMD =1).
Page 200 GD32G553 User Manual Set by hardware when Deep-sleep / standby reset generated. Reset by writing 1 to the RSTFC bit. 0: No Low-power management reset generated 1: Low-power management reset generated WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated.
Page 201: Clock Configuration Register 1 (Rcu_Cfg1)
GD32G553 User Manual Reset by writing 1 to the RSTFC bit. 0: No option byte loader reset generated 1: Option byte loader reset generated 22:2 Reserved Must be kept at reset value. IRC32KSTB IRC32K stabilization flag Set by hardware to indicate if the IRC32K output clock is stable and ready for use.
Page 202: Clock Configuration Register 2 (Rcu_Cfg2)
GD32G553 User Manual 00: CK_APB1 selected as USART2 source clock 01: CK_SYS selected as USART2 source clock 10: CK_LXTAL selected as USART2 source clock 11: CK_IRC8M selected as USART2 source clock 19:18 USART1SEL[1:0] USART1 clock source selection Set and reset by software to control the USART1 clock source...
Page 203 GD32G553 User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HRTIME Reserved ADC3SEL[1:0] ADC0_1_2SEL[1:0] Reserved Reserved QSPISEL[1:0] RSEL TRNGPSC[3:0] Reserved LPTIMERSEL[1:0] Reserved I2C3SEL[1:0] I2C2SEL[1:0] I2C1SEL[1:0] I2C0SEL[1:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 204 GD32G553 User Manual 0001: Reserved 0010: CK_PLLQ / 2 0011: CK_PLLQ / 3 0100: CK_PLLQ / 4 … 1111: CK_PLLQ / 15 Reserved Must be kept at reset value. 10:9 LPTIMERSEL[1:0] LPTIMER clock source selection Set and reset by software to control the LPTIMER clock source.
Page 205: Exti Introduction Interrupt / Event Controller (Exti)
GD32G553 User Manual EXTI introduction Interrupt / event controller (EXTI) 5.1. Overview ® Cortex -M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. More details about ®...
Page 206: Table 5-1. Nvic Exception Types In Cortex ® -M33
GD32G553 User Manual ® Table 5-1. NVIC exception types in Cortex -M33 Vector Exception Type Priority (a) Vector Address Description Number 0x0000_0000 Reserved 0x0000_0004 Reset Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management...
Page 207 GD32G553 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number DMA0 channel2 global interrupt 0x0000_0074 IRQ 13 IRQ 14 DMA0 channel3 global interrupt 0x0000_0078 IRQ 15 DMA0 channel4 global interrupt 0x0000_007C IRQ 16 DMA0 channel5 global interrupt 0x0000_0080...
Page 208 GD32G553 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number ADC2 global interrupt 0x0000_00FC IRQ 47 IRQ 48 SYSCFG interrupt 0x0000_0100 LPTIMER global interrupt and wakeup through IRQ 49 0x0000_0104 EXTI line35 interrupt IRQ 50 TIMER4 global interrupt...
Page 209 GD32G553 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number TIMER19 trigger and commutation interrupt / TIMER19 direction change interrupt / TIMER19 0x0000_017C IRQ 79 Index IRQ 80 TIMER19 capture compare interrupt 0x0000_0180 IRQ 81 FPU global interrupt...
Page 210 GD32G553 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number CAN1 interrupt for message buffer 0x0000_0214 IRQ 117 CAN1 interrupt for bus off / bus off done IRQ 118 0x0000_0218 CAN1 interrupt for error IRQ 119 0x0000_021C CAN1 interrupt for error in fast transmission...
Page 211: External Interrupt And Event (Exti) Block Diagram
GD32G553 User Manual 5.4. External interrupt and event (EXTI) block diagram Figure 5-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~38 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 5.5. External Interrupt and Event function overview The EXTI contains up to 39 independent edge detectors and generates interrupts request or event to the processer.
Page 212 GD32G553 User Manual Table 5-3 EXTI source EXTI Line Source Number PA0 / PB0 / PC0 / PD0 / PE0 / PF0 / PG0 PA1 / PB1 / PC1 / PD1 / PE1 / PF1 / PG1 PA2 / PB2 / PC2 / PD2 / PE2 / PF2 / PG2...
Page 213: Register Definition Register Definition
GD32G553 User Manual 5.6. Register definition Register definition EXTI base address: 0x4001 0400 Interrupt enable register 0 (EXTI_INTEN0) 5.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). INTEN31 INTEN30 INTEN29 INTEN28 INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16...
Page 214: Falling Edge Trigger Enable Register 0 (Exti_Ften0)
GD32G553 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). RTEN31 RTEN30 RTEN29 RTEN28 RTEN27 RTEN26 RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8...
Page 215: Pending Register 0 (Exti_Pd0)
GD32G553 User Manual Bits Fields Descriptions Interrupt/Event software trigger bit x (x = 0…31) 31:0 SWIEVx 0: Deactivate the EXTIx software interrupt/event request 1: Activate the EXTIx software interrupt/event request Pending register 0 (EXTI_PD0) 5.6.6. Address offset: 0x14 Reset value: undefined This register has to be accessed by word (32-bit).
Page 216: Event Enable Register 1 (Exti_Even1)
GD32G553 User Manual Event enable register 1 (EXTI_EVEN1) 5.6.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved EVEN38 EVEN37 EVEN36 EVEN35 EVEN34 EVEN33 EVEN32 Bits Fields Descriptions 31:7 Reserved Must be kept at reset value.
Page 217: Software Interrupt Event Register 1 (Exti_Swiev1)
GD32G553 User Manual Reserved Reserved FTEN38 FTEN37 FTEN36 FTEN35 FTEN34 FTEN33 FTEN32 Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. Falling edge trigger enable x (x = 32…38) FTENx 0: Falling edge of linex is invalid 1: Falling edge of linex is valid as an interrupt/event request Software interrupt event register 1 (EXTI_SWIEV1) 5.6.11.
Page 218 GD32G553 User Manual rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. Interrupt pending status x (x = 32…38) 0: EXTI linex is not triggered 1: EXTI linex is triggered. This bit is cleared to 0 by writing 1 to it...
Page 219: Trigger Selection Controller (Trigsel)
GD32G553 User Manual Trigger selection controller (TRIGSEL) 6.1. Overview The trigger selection controller (TRIGSEL) allows software to select the trigger input signal for various peripherals. TRIGSEL provides a flexible mechanism, there are up to 243 trigger input signals could be selected. Each peripheral corresponding to the independent trigger selection controller.
Page 220: Internal Connect
GD32G553 User Manual Figure 6-1. TRIGSEL main composition example Trigger Select Trigger input 0 Trigger input 1 Trigger output 2 Peripheral_x Trigger output 1 Trigger output 0 Trigger input n INSELx Trigger Register 6.4. Internal connect The TRIGSEL allows software to select the trigger input for peripherals. The Figure 6-1.
Page 221 GD32G553 User Manual fields bits value trigger input selection 0x0c TRIGSEL_IN10 0x0d TRIGSEL_IN11 0x0e TRIGSEL_IN12 0x0f TRIGSEL_IN13 0x10 TIMER0_TRGO0 0x11 TIMER0_TRGO1 0x12 TIMER0_CH0 0x13 TIMER0_CH1 0x14 TIMER0_CH2 0x15 TIMER0_CH3 0x16 TIMER0_MCH0 0x17 TIMER0_MCH1 0x18 TIMER0_MCH2 0x19 TIMER0_MCH3 0x1a-0x1f Reserved 0x20...
Page 222 GD32G553 User Manual fields bits value trigger input selection 0x3a TIMER6_TRGO0 0x3b TIMER7_TRGO0 0x3c TIMER7_TRGO1 0x3d TIMER7_CH0 0x3e TIMER7_CH1 0x3f TIMER7_CH2 0x40 TIMER7_CH3 0x41 TIMER7_MCH0 0x42 TIMER7_MCH1 0x43 TIMER7_MCH2 0x44 TIMER7_MCH3 0x45-0x4a Reserved 0x4b TIMER7_ETI 0x4c TIMER14_TRGO0 0x4d TIMER14_CH0 0x4e...
Page 223 GD32G553 User Manual fields bits value trigger input selection 0x72 TIMER7_BKIN2 0x73 TIMER14_BKIN0 0x74 TIMER15_BKIN0 0x75 TIMER16_BKIN0 0x76 TIMER19_BKIN0 0x77 TIMER19_BKIN1 0x78 TIMER19_BKIN2 0x79 LPTIMER_OUT 0x7a LPTIMER_ETI 0x7b HRTIMER_SCOUT 0x7c HRTIMER_SCIN 0x7d HRTIMER_ADCTRIG0 0x7e HRTIMER_ADCTRIG1 0x7f HRTIMER_ADCTRIG2 0x80 HRTIMER_ADCTRIG3 0x81...
Page 224 GD32G553 User Manual fields bits value trigger input selection 0x9e ADC2_WD1_OUT 0x9f ADC2_WD2_OUT 0xa0 ADC3_WD0_OUT 0xa1 ADC3_WD1_OUT 0xa2 ADC3_WD2_OUT 0xa3 HXTAL_DIV32_TRIG 0xa4 IRC32K_TRIG 0xa5 LXTAL_TRIG 0xa6 CKOUT_TRIG 0xa7 EXTI2_TRIG 0xa8 EXTI3_TRIG 0xa9 EXTI9_TRIG 0xaa EXTI10_TRIG 0xab EXTI11_TRIG 0xac EXTI15_TRIG 0xad...
Page 225: Table 6-2. Trigsel Input And Output Mapping
GD32G553 User Manual fields bits value trigger input selection 0xc7~0xde reserved 0xdf HRTIMER_ST0_CH0 0xe0 HRTIMER_ST0_CH1 0xe1 HRTIMER_ST1_CH0 0xe2 HRTIMER_ST1_CH1 0xe3 HRTIMER_ST2_CH0 0xe4 HRTIMER_ST2_CH1 0xe5 HRTIMER_ST3_CH0 0xe6 HRTIMER_ST3_CH1 0xe7 HRTIMER_ST4_CH0 0xe8 HRTIMER_ST4_CH1 0xe9 HRTIMER_ST5_CH0 0xea HRTIMER_ST5_CH1 0xeb HRTIMER_ST6_CH0 0xec HRTIMER_ST6_CH1 0xed...
Page 226 GD32G553 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TRIGSEL_IN6 TRIGSEL_IN7 TRIGSEL_EXTOUT_ Output0 TRIGSEL_OUT4 TRIGSEL_IN8 Output1 TRIGSEL_OUT5 TRIGSEL_IN9 TRIGSEL_IN10 TRIGSEL_IN11 TRIGSEL_EXTOUT_ Output0 TRIGSEL_OUT6 TRIGSEL_IN12 Output1 TRIGSEL_OUT7 TRIGSEL_IN13 TIMER0_TRGO0 TIMER0_TRGO1 Output0 ADC0_ROUTRG TRIGSEL_ADC0 TIMER0_CH0 Output1 ADC0_INSTRG TIMER0_CH1 TIMER0_CH2...
Page 227 GD32G553 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER4_CH2 TIMER4_CH3 TRIGSEL_TIMER16B Output0 TIMER16_BRKIN0 TIMER4_ETI RKIN TIMER5_TRGO0 TIMER6_TRGO0 Output0 TIMER19_BRKIN0 TIMER7_TRGO0 TRIGSEL_TIMER19B Output1 TIMER19_BRKIN1 TIMER7_TRGO1 RKIN Output2 TIMER19_BRKIN2 TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 CAN0_EX_TIME_TIC TRIGSEL_CAN0 Output0 TIMER7_CH3 TIMER7_MCH0 TIMER7_MCH1...
Page 228 GD32G553 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER7_BKIN1 TIMER7_BKIN2 TRIGSEL_TIMER7_E Output0 TIMER7_ETI TIMER14_BKIN0 TIMER15_BKIN0 TIMER16_BKIN0 TIMER19_BKIN0 TRIGSEL_TIMER19_ Output0 TIMER19_ETI TIMER19_BKIN1 TIMER19_BKIN2 LPTIMER_OUT LPTIMER_ETI TRIGSEL_HPDF Output0 HPDF_ITRG HRTIMER_SCOUT HRTIMER_SCIN HRTIMER_ADCTRIG0 HRTIMER_ADCTRIG1 TRIGSEL_TIMER0ITI Output0 TIMER0_ITI14 HRTIMER_ADCTRIG2 HRTIMER_ADCTRIG3...
Page 229 GD32G553 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output ADC2_WD1_OUT ADC2_WD2_OUT TRIGSEL_TIMER19I Output0 TIMER19_ITI14 ADC3_WD0_OUT TI14 ADC3_WD1_OUT ADC3_WD2_OUT HXTAL_DIV32_TRIG Output0 DAC0_EXTRIG TRIGSEL_DAC0 IRC32K_TRIG Output1 DAC0_EXTRIG LXTAL_TRIG CKOUT_TRIG EXTI2_TRIG Output0 DAC1_EXTRIG TRIGSEL_DAC1 EXTI3_TRIG Output1 DAC1_EXTRIG EXTI9_TRIG EXTI10_TRIG EXTI11_TRIG...
Page 230 GD32G553 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output HRTIMER_ST1_CH0 Output0 TRIGSEL_CLA_IN3 HRTIMER_ST1_CH1 TRIGSEL_CLA_1 Output1 TRIGSEL_CLA_IN4 HRTIMER_ST2_CH0 Output2 TRIGSEL_CLA_IN5 HRTIMER_ST2_CH1 HRTIMER_ST3_CH0 HRTIMER_ST3_CH1 Output0 TRIGSEL_CLA_IN6 HRTIMER_ST4_CH0 TRIGSEL_CLA_2 Output1 TRIGSEL_CLA_IN7 HRTIMER_ST4_CH1 Output2 TRIGSEL_CLA_IN8 HRTIMER_ST5_CH0 HRTIMER_ST5_CH1 Output0 TRIGSEL_CLA_IN9 HRTIMER_ST6_CH0 TRIGSEL_CLA_3...
Page 231 GD32G553 User Manual When illegal data is selected for these outputs, the output will be selected as 0.
Page 232: Register Definition
GD32G553 User Manual 6.5. Register definition TRIGSEL base address: 0x4001 8400 Trigger selection for EXTOUT register 0 (TRIGSEL_EXTOUT_0) 6.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock.
Page 233: Trigger Selection For Extout Register 2 (Trigsel_Extout_2)
GD32G553 User Manual INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_EXTOUT_1 register. 0: TRIGSEL_EXTOUT_1 register write is enabled.
Page 234: Trigger Selection For Extout Register 3 (Trigsel_Extout_3)
GD32G553 User Manual These bits are used to select trigger input signal connected to output1. The output is used as the source of TRIGSEL_OUT5 (external output5 signal). For the detailed configuration, please refer to Table 6-1. Trigger input bit fields selection.
Page 235: Trigger Selection For Adc1 Register (Trigsel_Adc1)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_ADC0 register.
Page 236: Trigger Selection For Adc2 Register (Trigsel_Adc2)
GD32G553 User Manual disables write access to TRIGSEL_ADC1 register. 0: TRIGSEL_ADC1 register write is enabled. 1: TRIGSEL_ADC1 register write is disabled. 30:16 Reserved Must be kept at reset value. 15:8 INSEL1[7:0] Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1. The output is used as the souce of ADC1_INSTRG (ADC1 insert sequence) trigger input.
Page 237: Trigger Selection For Adc3 Register (Trigsel_Adc3)
GD32G553 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of ADC2_ROUTRG(ADC2 routine sequence) trigger input. For the detailed configuration, please refer to Table 6-1.
Page 238: Trigger Selection For Timer7_Brkin Register (Trigsel_Timer7Brkin)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved INSEL2[7:0] INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER0BRKIN register.
Page 239: Trigger Selection For Timer14_Brkin Register (Trigsel_Timer14Brkin)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER7BRKIN register. 0: TRIGSEL_TIMER7BRKIN register write is enabled. 1: TRIGSEL_TIMER7BRKIN register write is disabled.
Page 240: Trigger Selection For Timer15_Brkin Register (Trigsel_Timer15Brkin)
GD32G553 User Manual 30:8 Reserved Must be kept at reset value. INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER14BRKIN0 trigger input. For the detailed configuration, please refer to Table 6-1.
Page 241: Trigger Selection For Timer19_Brkin Register (Trigsel_Timer19Brkin)
GD32G553 User Manual Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER16BRKIN register. 0: TRIGSEL_TIMER16BRKIN register write is enabled.
Page 242: Trigger Selection For Can0 Register (Trigsel_Can0)
GD32G553 User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER19BRKIN0 trigger input. For the detailed configuration, please refer to Table 6-1. Trigger input bit fields selection.
Page 243: Trigger Selection For Can2 Register (Trigsel_Can2)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_CAN1 register. 0: TRIGSEL_CAN1 register write is enabled. 1: TRIGSEL_CAN1 register write is disabled.
Page 244: Trigger Selection For Timer1_Eti Register (Trigsel_Timer1Eti)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER0ETI register.
Page 245: Trigger Selection For Timer2_Eti Register (Trigsel_Timer2Eti)
GD32G553 User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER1_ETI trigger input. For the detailed configuration, please refer to Table 6-1. Trigger input bit fields selection.
Page 246: Trigger Selection For Timer4_Eti Register (Trigsel_Timer4Eti)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER3ETI register. 0: TRIGSEL_TIMER3ETI register write is enabled. 1: TRIGSEL_TIMER3ETI register write is disabled.
Page 247: Trigger Selection For Timer19_Eti Register (Trigsel_Timer19Eti)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER7ETI register.
Page 248: Trigger Selection For Hpdf_Itrg Register (Trigsel_Hpdf)
GD32G553 User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER19_ETI trigger input. For the detailed configuration, please refer to Table 6-1. Trigger input bit fields selection.
Page 249: Trigger Selection For Timer1_Iti14 Register (Trigsel_Timer1Iti14)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER0ITI14 register. 0: TRIGSEL_TIMER0ITI14 register write is enabled. 1: TRIGSEL_TIMER0ITI14 register write is disabled.
Page 250: Trigger Selection For Timer3_Iti14 Register (Trigsel_Timer3Iti14)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER2ITI14 register.
Page 251: Trigger Selection For Timer4_Iti14 Register (Trigsel_Timer4Iti14)
GD32G553 User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER3_ITI14 trigger input. For the detailed configuration, please refer to Table 6-1. Trigger input bit fields selection.
Page 252: Trigger Selection For Timer14_Iti14 Register (Trigsel_Timer14Iti14)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER7ITI14 register. 0: TRIGSEL_TIMER7ITI14 register write is enabled. 1: TRIGSEL_TIMER7ITI14 register write is disabled.
Page 253: Trigger Selection For Dac0 Register (Trigsel_Dac0)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER19ITI14 register.
Page 254: Trigger Selection For Dac1 Register (Trigsel_Dac1)
GD32G553 User Manual These bits are used to select trigger input signal connected to output1. The output is used as the source of DAC0_OUT1_EXTRIG (DAC0_OUT1 external trigger) input. For the detailed configuration, please refer to Table 6-1. Trigger input bit fields selection.
Page 255: Trigger Selection For Dac2 Register (Trigsel_Dac2)
GD32G553 User Manual Trigger selection for DAC2 register (TRIGSEL_DAC2) 6.5.36. Address offset: 0x98 Reset value: 0x0000 1010 This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_DAC2 register.
Page 256: Trigger Selection For Dac0 Extended Register (Trigsel_Extdac0)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_DAC3 register. 0: TRIGSEL_DAC3 register write is enabled. 1: TRIGSEL_DAC3 register write is disabled.
Page 257: Trigger Selection For Dac1 Extended Register (Trigsel_Extdac1)
GD32G553 User Manual 15:8 INSEL1[7:0] Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1. The output is used as the souce of DAC0_OUT1_ST_EXTRIG (DAC0_OUT1 sawtooth step- up/down external trigger) trigger input. For the detail configuration, please see Table 6-1.
Page 258: Trigger Selection For Dac2 Extended Register (Trigsel_Extdac2)
GD32G553 User Manual Trigger selection for DAC2 extended register (TRIGSEL_EXTDAC2) 6.5.40. Address offset: 0xA8 Reset value: 0x0000 1010 This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_EXTDAC2 register.
Page 259: Trigger Selection For Cla Register 0 (Trigsel_Cla_0)
GD32G553 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_EXTDAC3 register. 0: TRIGSEL_EXTDAC3 register write is enabled. 1: TRIGSEL_EXTDAC3 register write is disabled.
Page 260: Trigger Selection For Cla Register 1 (Trigsel_Cla_1)
GD32G553 User Manual 1: TRIGSEL_CLA_0 register write is disabled. 30:24 Reserved Must kept at reset value. 23:16 INSEL2[7:0] Trigger input source selection for output2 These bits are used to select trigger input signal connected to output2. The output is used as the souce of TRIGSEL_CLA_IN2 trigger input. For the detail configuration, please see Table 6-1.
Page 261: Trigger Selection For Cla Register 2 (Trigsel_Cla_2)
GD32G553 User Manual These bits are used to select trigger input signal connected to output2. The output is used as the souce of TRIGSEL_CLA_IN5 trigger input. For the detail configuration, please see Table 6-1. Trigger input bit fields selection. 15:8...
Page 262: Trigger Selection For Cla Register 3 (Trigsel_Cla_3)
GD32G553 User Manual These bits are used to select trigger input signal connected to output2. The output is used as the souce of TRIGSEL_CLA_IN6 trigger input. For the detail configuration, please see Table 6-1. Trigger input bit fields selection. Trigger selection for CLA register 3 (TRIGSEL_CLA_3) 6.5.45.
Page 263 GD32G553 User Manual Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_CLA_4 register. 0: TRIGSEL_CLA_4 register write is enabled.
Page 264: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32G553 User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 107 general purpose I / O pins (GPIO), named PA0~PA15, PB0~PB15, PC0~PC15, PD0~PD15, PE0~PE15, PF0~PF15, PG0~PG10 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications.
Page 265: Figure 7-1. Basic Structure Of A Standard I/O Port Bit
GD32G553 User Manual the port is output (GPIO output or AFIO output), it can be configured as push-pull or open drain mode by GPIO output mode registers (GPIOx_OMODE). And the port max speed can be configured by GPIO output speed registers (GPIOx_OSPD). Each port can be configured as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up / pull- down registers (GPIOx_PUD).
Page 266: Gpio Pin Configuration
GD32G553 User Manual Figure 7-1. Basic structure of a standard I/O port bit Write Bit Operate Registers Output Output driver Control Read/Write Register Output Control Alternate Function Output protection Analog ( Input / Output ) I/O pin Alternate Function Input...
Page 267: External Interrupt / Event Lines
GD32G553 User Manual  Reset input only: after option bytes loading NRST_MODE = 1.  GPIO PG10 mode: after option bytes loading NRST_MODE = 2. The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen.
Page 268: Output Configuration
GD32G553 User Manual shows the input configuration. Figure 7-2. Input configuration Figure 7-2. Input configuration Alternate Function Input protection Input Read I/O pin Status Register Schmitt trigger Input driver Output configuration 7.3.6. When GPIO pin is configured as output: ...
Page 269: Analog Configuration
GD32G553 User Manual Analog configuration 7.3.7. When GPIO pin is used as analog configuration:  The weak pull-up and pull-down resistors are disabled.  The output buffer is disabled.  The schmitt trigger input is disabled.  The port input status register of this I / O port bit is “0”.
Page 270: Gpio Locking Function
GD32G553 User Manual Figure 7-5. Alternate function configuration Output driver Alternate Function Output Output Control protection I/O pin Alternate Function Input Schmitt trigger Input driver GPIO locking function 7.3.9. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD and GPIOx_AFSELy (y=0, 1).
Page 271: Input Filtering
GD32G553 User Manual Input filtering 7.3.12. The type of input filtering for each GPIO pin can be select by configuring GPIOx_IFTP register. In the case of GPIO, filtering can be specified to synchronize only to CK_AHB or through the sampling window. For pins configured as peripheral input, in addition to synchronization to CK_AHB or through the sampling window, the input can also be asynchronous.
Page 272 GD32G553 User Manual frequency relative to CK_AHB. The sampling period is determined by FLPRDx in register GPIOx_IFL. The sampling period can be configured as 8 input signal groups. For example, GPIO0 to GPIO7 use FLPRD0, GPIO8 to GPIO15 use FLPRD1.
Page 273: Figure 7-7. Input Filtering Clock Cycle
GD32G553 User Manual =2×T =2×10ns=20ns CK_AHB =6×2×T =6×20ns=120ns CK_AHB  To illustrate the asynchronous nature of the input relative to the sampling period and the system clock, an additional smpling period and CK_AHB cycle may be required to detect the change of input signal.
Page 274: Register Definition
GD32G553 User Manual 7.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOE base address: 0x4800 1000 GPIOF base address: 0x4800 1400 GPIOG base address: 0x4800 1800 Port control register (GPIOx_CTL, x=A..G)
Page 275 GD32G553 User Manual Refer to CTL0[1:0] description 21:20 CTL10[1:0] Pin 10 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description...
Page 276: Port Output Mode Register (Gpiox_Omode, X=A
GD32G553 User Manual Port output mode register (GPIOx_OMODE, x=A..G) 7.4.2. Address offset: 0x04 Reset value: 0xABFF FFFF for port A; 0xFFFF FEBF for port B; 0xFFFF FFFF for others. This register has to be accessed by word (32-bit). Reserved OM15...
Page 277: Port Output Speed Register (Gpiox_Ospd, X=A
GD32G553 User Manual These bits are set and cleared by software. Refer to OM0 description Pin 6 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software.
Page 278 GD32G553 User Manual These bits are set and cleared by software. Refer to OSPD0[1:0] description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by software.
Page 279: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32G553 User Manual Refer to OSPD0[1:0] description OSPD2[1:0] Pin 2 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software.
Page 280 GD32G553 User Manual 23:22 PUD11[1:0] Pin 11 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 21:20 PUD10[1:0] Pin 10 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description...
Page 281: Port Input Status Register (Gpiox_Istat, X=A
GD32G553 User Manual 11: Reserved Port input status register (GPIOx_ISTAT, x=A..G) 7.4.5. Address offset: 0x10 Reset value: 0xABFF FFFF for port A; 0xFFFF FEBF for port B; 0xFFFF FFFF for others. This register has to be accessed by word (32-bit).
Page 282: Port Bit Operate Register (Gpiox_Bop, X=A
GD32G553 User Manual Port bit operate register (GPIOx_BOP, x=A..G) 7.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8...
Page 283: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
GD32G553 User Manual Write 1→Write 0→Write 1→ Read 0→ Read 1 Note: The value of LKy(y=0..15) must be held during the LOCK Key writing sequence. 15:0 Port lock bit y(y=0..15) These bits are set and cleared by software. 0: Port configuration not locked 1: Port configuration locked Alternate function selected register 0 (GPIOx_AFSEL0, x=A..G)
Page 284: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
GD32G553 User Manual SEL1[3:0] Pin 1 alternate function selected These bits are set and cleared by software. Refer to SEL0[3:0] description SEL0[3:0] Pin 0 alternate function selected These bits are set and cleared by software. 0000: AF0 selected (reset value)
Page 285: Bit Clear Register (Gpiox_Bc, X=A
GD32G553 User Manual Refer to SEL8[3:0] description 15:12 SEL11[3:0] Pin 1 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description 11:8 SEL10[3:0] Pin 10 alternate function selected These bits are set and cleared by software.
Page 286: Port Bit Toggle Register (Gpiox_Tg, X=A
GD32G553 User Manual 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x=A..G) 7.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 287: Input Filtering Type Register (Gpiox_Iftp, X=A
GD32G553 User Manual FF: FLPRDx = CK_AHB / 510 FLPRD0 Filter sampling period for GPIO1 to GPIO7: 00: FLPRDx = CK_AHB 01: FLPRDx = CK_AHB / 2 02: FLPRDx = CK_AHB / 4 ..FF: FLPRDx = CK_AHB / 510 Input filtering type register (GPIOx_IFTP, x=A…G)
Page 288 GD32G553 User Manual 19:18 IFTP9[1:0] Pin 9 input filtering type bits These bits are set and cleared by software. Refer to IFTP0[1:0] description 17:16 IFTP8[1:0] Pin 8 input filtering type bits These bits are set and cleared by software. Refer to IFTP0[1:0] description...
Page 289: Direct Memory Access Controller (Dma)
GD32G553 User Manual Direct memory access controller (DMA) 8.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 290: Block Diagram
GD32G553 User Manual 8.3. Block diagram Figure 8-1. Block diagram of DMA AHB slave interface Configuration … dma_req Channel 6 AHB master dma_ack interface Channel 2 dma_req Master dma_ack Port Channel 1 dma_req dma_ack Channel 0 dma_req dma_ack Memory control state &...
Page 291: Table 8-1. Dma Transfer Operation
GD32G553 User Manual Table 8-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8...
Page 292: Peripheral Handshake
GD32G553 User Manual The CNT bits in the DMA_CHxCNT register control how many data to be transmitted on the channel and must be configured before enable the CHEN bit in the register. During the transmission, the CNT bits indicate the remaining number of data items to be transferred.
Page 293: Address Generation
GD32G553 User Manual the software priority and the hardware priority. The arbiter determines which channel is selected to respond according to the following priority rules:  Software priority: Four levels, including low, medium, high and ultra-high by configuring the PRIO bits in the DMA_CHxCTL register.
Page 294: Interrupt
GD32G553 User Manual 3. Configure the CMEN bit in the DMA_CHxCTL register to enable/disable the circular mode. 4. Configure the PRIO bits in the DMA_CHxCTL register to set the channel software priority. 5. Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register.
Page 295: Dma Request Mapping
GD32G553 User Manual DMA request mapping 8.4.9. The DMA requests of a channel are coming from the AHB/APB peripherals through the corresponding channel output of DMAMUX request multiplexer, refer to Table 9-3. Request multiplexer input mapping.
Page 296: Register Definition
GD32G553 User Manual 8.5. Register definition DMA base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Interrupt flag register (DMA_INTF) 8.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ERRIF6 HTFIF6...
Page 297: Channel X Control Register (Dma_Chxctl)
GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0...
Page 298 GD32G553 User Manual 0: Disable Memory to Memory mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’.
Page 299: Channel X Counter Register (Dma_Chxcnt)
GD32G553 User Manual Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt...
Page 300: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32G553 User Manual transaction can be issued whether the channel is enabled or not. Once the transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode.
Page 301 GD32G553 User Manual When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these...
Page 302: Dma Request Multiplexer (Dmamux)
GD32G553 User Manual DMA request multiplexer (DMAMUX) 9.1. Overview DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.
Page 303: Block Diagram
GD32G553 User Manual 9.3. Block diagram Figure 9-1. Block diagram of DMAMUX Request multiplexer Slave Port Channel 13 Channel 2 Channel 1 Peri_reqx To DMA controller: Channel 0 Reqx_out Sync Counter underrun: Reqx_in Evtx_out Configuration Register Input selector Synchronization inputs:...
Page 304: Dmamux Signals
GD32G553 User Manual  DMAMUX request generator. Trigger inputs (Trgx_in) source from internal or external signals. DMAMUX signals 9.4.1. Table 9-1. DMAMUX signals Signal name Discription DMAMUX request multiplexer inputs (from peripheral requests and request Reqx_in generator channels) Peri_reqx DMAMUX DMA request line inputs from peripherals...
Page 305: Figure 9-2. Synchronization Mode
GD32G553 User Manual If the channel event generation is enabled by setting EVGEN bit, the number of DMA requests before an output event generation is NBR[4:0] + 1. Note: The NBR[4:0] bits value shall only be written by software when both synchronization enable bit SYNCEN and event generation enable EVGEN bit of the corresponding request multiplexer channel x are disabled.
Page 306: Figure 9-3. Event Generation
GD32G553 User Manual Note: If a synchronization input event occurs when there is no pending selected input DMA request line, the input event is discarded. The following asserted input request lines will not be routed to the DMAMUX multiplexer channel output until a synchronization input event occurs again.
Page 307: Dmamux Request Generator
GD32G553 User Manual there will be a synchronization overrun due to the absence of a DMA acknowledge (that is, no served request) received from the DMA controller. DMAMUX request generator 9.4.3. The DMAMUX request generator produces DMA requests upon trigger input event. Its component unit is the request generator channels.
Page 308: Channel Configurations
GD32G553 User Manual Channel configurations 9.4.4. The following sequence should be followed to configure a DMAMUX channel y and the related DMA channel x: Set and configure the DMA channel x completely, except enabling the channel x. Set and configure the related DMAMUX channel y completely.
Page 309: Dmamux Mapping
GD32G553 User Manual DMAMUX mapping 9.4.6. Request multiplexer input mapping A DMA request is sourced either from the peripherals or from the DMAMUX request generator, the sources can refer to Table 9-3. Request multiplexer input mapping, configured by the MUXID[7:0] bits in the DMAMUX_RM_CHxCFG register for the DMAMUX request multiplexer channel x.
Page 310 GD32G553 User Manual Request multiplexer channel input identification Source MUXID[7:0] UART3_RX UART3_TX UART4_RX UART4_TX ADC1 ADC2 ADC3 QSPI DAC1_CH0 DAC1_CH1 TIMER0_CH0 TIMER0_CH1 TIMER0_CH2 TIMER0_CH3 TIMER0_CH0N TIMER0_CH1N TIMER0_CH2N TIMER0_CH3N TIMER0_ UP TIMER0_TI TIMER0_CO TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TIMER7_CH3 TIMER7_CH0N TIMER7_CH1N TIMER7_CH2N TIMER7_CH3N...
Page 311 GD32G553 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER2_CH1 TIMER2_CH2 TIMER2_CH3 TIMER2_ UP TIMER2_TI TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_CH3 TIMER3_ UP TIMER3_TI TIMER4_CH0 TIMER4_CH1 TIMER4_CH2 TIMER4_CH3 TIMER4_ UP TIMER4_TI TIMER14_CH0 TIMER14_CH1 TIMER14_CH0N TIMER14_ UP TIMER14_ TI TIMER14_ CO TIMER15_CH0...
Page 312: Table 9-4. Trigger Input Mapping
GD32G553 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER19_ CO CAU_IN CAU_OUT HRTIMER_M HRTIMER_0 HRTIMER_1 HRTIMER_2 HRTIMER_3 HRTIMER_4 HRTIMER_5 HRTIMER_6 HRTIMER_7 DAC2_CH0 DAC2_CH1 DAC3_CH0 DAC3_CH1 HPDF_FLT0 HPDF_FLT1 HPDF_FLT2 HPDF_FLT3 FAC_RD FAC_WR TMU_RD TMU_WR CAN0 CAN1 CAN2 Trigger input mapping...
Page 313: Table 9-5. Synchronization Input Mapping
GD32G553 User Manual Trigger input identification Source TID[4:0] EXTI_3 EXTI_4 EXTI_5 EXTI_6 EXTI_7 EXTI_8 EXTI_9 EXTI_10 EXTI_11 EXTI_12 EXTI_13 EXTI_14 EXTI_15 Evtx_out0 Evtx_out1 Evtx_out2 Evtx_out3 LPTIMER_OUT Synchronization input mapping The synchronization input is selected by SYNCID[4:0] bits in the DMAMUX_RM_CHxCFG register, the sources can refer to Table 9-5.
Page 314 GD32G553 User Manual Synchronization input Source identification SYNCID[4:0] EXTI_14 EXTI_15 Evtx_out0 Evtx_out1 Evtx_out2 Evtx_out3 LPTIMER_OUT...
Page 315: Register Definition
GD32G553 User Manual 9.5. Register definition DMAMUX base address: 0x4002 0800 Request multiplexer channel configuration register 9.5.1. (DMAMUX_RM_CHxCFG) x = 0...13, where x is a channel number Address offset: 0x00 + 0x04 × x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 316: Request Multiplexer Channel Interrupt Flag Register (Dmamux_Rm_Intf)
GD32G553 User Manual 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt MUXID[7:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) 9.5.2. Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 317: Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
GD32G553 User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:0 SOIFCx Clear bit for synchronization overrun event flag of request multiplexer channel x (x=0..13) Writing 1 clears the corresponding overrun flag SOIFx in the DMAMUX_RM_INTF register.
Page 318: Request Generator Interrupt Flag Register (Dmamux_Rg_Intf)
GD32G553 User Manual 1: Enable interrupt Reserved Must be kept at reset value. TID[4:0] Trigger input identification Selects the DMA request trigger input source. Request generator interrupt flag register (DMAMUX_RG_INTF) 9.5.5. Address offset: 0x140 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 319 GD32G553 User Manual TOIFCx Clear bit for trigger overrun event flag of request generator channel x (x=0..3) Writing 1 in each bit clears the corresponding overrun flag TOIFx in the DMAMUX_RG_INTF register.
Page 320: Cyclic Redundancy Checks Management Unit (Crc)
GD32G553 User Manual Cyclic redundancy checks management unit (CRC) 10.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial 10.2.
Page 321: Function Overview
GD32G553 User Manual Function overview 10.3.  CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 322: Register Definition
GD32G553 User Manual 10.4. Register definition CRC base address: 0x4002 3000 Data register (CRC_DATA) 10.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 323: Control Register (Crc_Ctl)
GD32G553 User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control register (CRC_CTL) 10.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O...
Page 324: Polynomial Register (Crc_Poly)
GD32G553 User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. Polynomial register (CRC_POLY) 10.4.5.
Page 325: Configurable Logic Array (Cla)
GD32G553 User Manual Configurable Logic Array (CLA) Overview 11.1. The configurable logic array provides 256 programmable digital logic operations for external pins, CMP, ADC and timers without intervention from the CPU. Four independent CLA units are implemented in this module. Each CLA unit supports configurable asynchronous and synchronous output for GPIO pins.
Page 326: Function Overview
GD32G553 User Manual Function overview 11.4. Four identical CLA units are inplemented in this module. Two SIGS are implemented in each CLA units. In addition, a LCU is included in each CLA units. CLA input Signal Selector 11.4.1. Each CLA unit includes two Signal Selector: SIGS0 and SIGS1. The input of each SIGS...
Page 327: Lcu Control
GD32G553 User Manual 0100 TRIGSEL_CLA_IN11 TRIGSEL_CLA_IN11 TRIGSEL_CLA_IN11 TRIGSEL_CLA_IN11 0101 TRIGSEL_CLA_IN3 TRIGSEL_CLA_IN1 TRIGSEL_CLA_IN0 TRIGSEL_CLA_IN0 0110 TRIGSEL_CLA_IN4 TRIGSEL_CLA_IN2 TRIGSEL_CLA_IN2 TRIGSEL_CLA_IN1 0111 TRIGSEL_CLA_IN5 TRIGSEL_CLA_IN5 TRIGSEL_CLA_IN4 TRIGSEL_CLA_IN3 1000 CLAIN1 (PB3) CLAIN6 (PB8) CLAIN2 (PB4) CLAIN0 (PA15) 1001 CLAIN3 (PB5) CLAIN7 (PB9) CLAIN3 (PB5) CLAIN1 (PB3)
Page 328: Cla Output
GD32G553 User Manual when {IN0, IN1 IN2} == 3’b100, the result of (IN0^IN1^IN2) is 1’b1, so bit 4 of LCU [7:0] = 1; when {IN0, IN1 IN2} == 3’b101, the result of (IN0^IN1^IN2) is 1’b0, so bit 5 of LCU [7:0] = 0;...
Page 329: Figure 11-2. Cla Interrupt Logic
GD32G553 User Manual Figure 11-2. CLA interrupt logic...
Page 330: Register Definition
GD32G553 User Manual Register definition 11.5. CLA base address: 0x4003 8000 Global control register (CLA_GCTL) 11.5.1. Address offset: 0x00 Reset value: 0x0000 0000(must be power reset) This register has to be accessed by word(32-bit) Reserved Reserved CLA3EN CLA2EN CLA1EN CLA0EN...
Page 331 GD32G553 User Manual Reserved Reserved CLA3PIE CLA3NIE CLA2PIE CLA2NIE CLA1PIE CLA1NIE CLA0PIE CLA0NIE Bits Fields Descriptions 31:8 Reserved Must be kept at reset value CLA3PIE CLA3 unit posedge interrupt enable Software set and cleared 0: CLA3 unit posedge interrupt is disabled 1: CLA3 unit posedge interrupt is enabled.
Page 332: Interrupt Flag Register (Cla_Intf)
GD32G553 User Manual Software set and cleared 0: CLA0 unit posedge interrupt is disabled 1: CLA0 unit posedge interrupt is enabled. An interrupt is generated when the CLA0PF bit is set. CLA0NIE CLA0 unit negedge interrupt enable Software set and cleared 0: CLA0 unit negedge interrupt is disabled 1: CLA0 unit negedge interrupt is enabled.
Page 333: Status Register (Cla_Stat)
GD32G553 User Manual CLA1PF CLA1 unit posedge flag Hareware set and software cleared 0: A CLA1 output posedge has not been detected 1: A CLA1 output posedge has been detected CLA1NF CLA1 unit negedge flag Hareware set and software cleared...
Page 334: Signal Selection Register (Clax_Sigs) (X = 0
GD32G553 User Manual CLA1OUT CLA1 unit output state Hardware set and cleared 0: The current logic level of CLA1 unit is LOW 1: The current logic level of CLA1 unit is HIGH CLA0OUT CLA0 unit output state Hardware set and cleared...
Page 335: Control Register (Clax_Ctl) (X=0
GD32G553 User Manual Reserved LCU[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value LCU[7:0] LCU control Software set and cleared These bits controll which logic function of the input0, input1 and input2 can be effected on the output Examples: IN1 | IN2: LCU = 8’b11101110...
Page 336 GD32G553 User Manual CPOL Clock polarity of Flip-flop Software set and cleared This bitfield must not be modified once the CLAx is enabled(CLAxEN = 1) 0: clock posedge is valid 1: clock negedge is valid CSEL[1:0] Flip-flop clock source selection...
Page 337: True Random Number Generator (Trng)
GD32G553 User Manual True random number generator (TRNG) 12.1. Overview The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise and it has been pre-certified NIST SP800-90B. 12.2. Characteristics  LFSR mode and NIST mode to generate random number.
Page 338: Function Overview
GD32G553 User Manual 12.4. Function overview Figure 12-1. TRNG block diagram AHB 32-bit Bus TRNG_CTL TRNG_STAT TRNG_DATA 32bit 32bit FIFO HCLK LFSR 128/256bit Clock Check Seed Check Conditioning (optional) TRNG_CLK 256/440bit post-process (optional) NIST Analog Seed mode HCLK domain Nist seed selection TRNG_CLK domain There are two modes in TRNG module, NIST mode and LFSR mode.
Page 339: Lfsr
GD32G553 User Manual LFSR 12.4.1. A Linear Feedback Shift Register is a sequential shift register with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary values. This operation will increase the entropy of the random number, and TRNG generates 32-bit data each time in this mode.
Page 340: Health Check
GD32G553 User Manual Table 12-1. ALGO configurations ALGO algorithm SHA1 SHA224 SHA256 valid length Health check 12.4.5. This component ensures the stable operation of TRNG and can quickly monitor the occurrence of errors. The health tests features of TRNG module following NIST SP800-90B. For more details about thresholds, refer to TRNG_HTCFG register.
Page 341: Nist Mode Fsm
GD32G553 User Manual detected, and if the interrupt bit of TRNG is asserted, an interrupt is generated.  When the replace test is enabled, the random numbers generated are only used to verify the functionality of the conditioning component. After the test is completed, the random numbers should be discarded and should not be used as true random numbers.
Page 342: Error Flags
GD32G553 User Manual is set.  A seed error occurs, and the SEIF and ERRSTA bits in the TRNG_STAT register are set.  A clock error occurs, and the CEIF and ERRSTA bits in the TRNG_STAT register are set. As required by the FIPS PUB 140-2, the first random data in data register should be saved but not be used.
Page 343: Register Definition
GD32G553 User Manual 12.5. Register definition TRNG base address: 0x4802 1800 Control register (TRNG_CTL) 12.5.1. Address offset: 0x00 Reset value: 0x0300 0410 This register has to be accessed by word (32-bit). CONDRS CTLLK Reserved NR[1:0] Reserved CLKDIV[3:0] INMOD OUTMOD ALGO[1:0]...
Page 344 GD32G553 User Manual 0: 256 bits 1: 440 bits OUTMOD Select random data width output of conditioning module 0: 128-bit 1: 256-bit conditioning module hash algorithm selection 13:12 ALGO[1:0] 00: SHA1 01: MD5 10: SHA224 11: SHA256 Reserved Must be kept at reset value.
Page 345: Status Register (Trng_Stat)
GD32G553 User Manual 0: Disable TRNG module (reduce power consuming) 1: Enable TRNG module Must be kept at reset value. Reserved Status register (TRNG_STAT) 12.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 346: Data Register (Trng_Data)
GD32G553 User Manual 1: Clock error is detected at current time. TRNG_CLK frequency is lower than 1/16 HCLK frequency. DRDY Random data ready status bit. This bit is cleared by reading the TRNG_DATA register and set when a new random number is generated.
Page 347 GD32G553 User Manual 25:16 APTTH[9:0] Adaptive proportion test threshold. Default 691. Must be kept at reset value. 15:7 Reserved RCTTH[6:0] Repetition count test threshold. Default 40.
Page 348: Cryptographic Acceleration Unit (Cau)
GD32G553 User Manual Cryptographic Acceleration Unit (CAU) 13.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ...
Page 349: Cau Data Type And Initialization Vectors
GD32G553 User Manual  8*32-bit input and output FIFO.  Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping.  Data can be transferred by DMA, CPU during interrupts, or without both of them.
Page 350: Initialization Vectors
GD32G553 User Manual Figure 13-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping Initialization vectors 13.3.2. The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks.
Page 351: Des / Tdes Cryptographic Acceleration Processor
GD32G553 User Manual Figure 13-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_GCMCC CAU_GCMCT STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 MCTXS0..7 XS0..7 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Configuration 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core（DES / TDES / AES）...
Page 352: Figure 13-4. Des/Tdes Ecb Encryption
GD32G553 User Manual DES / TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1.
Page 353: Figure 13-5. Des/Tdes Ecb Decryption
GD32G553 User Manual Figure 13-5. DES/TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES/TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 354: Figure 13-6. Des/Tdes Cbc Encryption
GD32G553 User Manual Figure 13-6. DES/TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES / TDES CBC decryption In DES/TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 355: Aes Cryptographic Acceleration Processor
GD32G553 User Manual Figure 13-7. DES/TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 13.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 356: Figure 13-8. Aes Ecb Encryption
GD32G553 User Manual Figure 13-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 357: Figure 13-10. Aes Cbc Encryption
GD32G553 User Manual AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the...
Page 358: Figure 13-11. Aes Cbc Decryption
GD32G553 User Manual plaintext is also obtained after data swapping according to the data type. The procedure of AES CBC mode decryption is illustrated in Figure 13-11. AES CBC decryption. Figure 13-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L)
Page 359 GD32G553 User Manual Figure 13-13. AES CTR encryption/decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois/counter mode (GCM) can be used to encrypt or authenticate message, and then ciphertext and tag can be obtained. This algorithm is based on AES CTR mode to ensure confidentiality.
Page 360 GD32G553 User Manual Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption/decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted/decrypted. Configure GCM_CCMPH[1:0] bits to ‘10’.
Page 361 GD32G553 User Manual 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled. (b) Configure the ALGM[3:0] bits to ‘1001’.
Page 362: Operating Modes
GD32G553 User Manual (q) Wait until the ONE flag is set to 1, and then read CAU_DO 4 times. The output corresponds to the authentication tag. (r) Disable the CAU AES-CFB mode The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice versa.
Page 363: Cau Dma Interface
GD32G553 User Manual Decryption 1. Disable the CAU by resetting the CAUEN bit in the CAU_CTL register. 2. Enable CAU power domain by setting the CORE1WAKE bit in the PMU_CTL1 register, and then enable CAU clock. 3. Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen.
Page 364: Cau Interrupts
GD32G553 User Manual DMA channel for output data has a higher priority than that channel for input data so that the output FIFO can be empty earlier than that the input FIFO is full. 13.7. CAU interrupts There are two types of interrupt registers in CAU, which are CAU_STAT1 and CAU_INTF. In CAU, the interrupt is used to indicate the situation of the input and output FIFO.
Page 365 GD32G553 User Manual or CCM mode, the context switch CAU_GCMCCMCTXSx (x = 0..7) and CAU_GCMCTXSx (x = 0..7) registers should also be stored. 5. Configure and process the new data block. 6. Restore the process before. Configure the CAU with the parameters stored before, and prepare the key and initialization vectors, and the context switch registers CAU_GCMCCMCTXSx (x = 0..7) and CAU_GCMCTXSx (x = 0..7) should also be...
Page 366: Register Definition
GD32G553 User Manual 13.9. Register definition CAU base address: 0x4802 1000 Control register (CAU_CTL) 13.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved NBPILB[3:0] ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH Reserved KEYM[1:0]...
Page 367 GD32G553 User Manual 13:10 Reserved Must be kept at reset value. KEYM[1:0] AES key size mode configuration, must be configured when BUSY=0 00: 128-bit key length 01: 192-bit key length 10: 256-bit key length 11: never use DATAM[1:0] Data swapping type mode configuration, must be configured when BUSY=0...
Page 368: Status Register 0 (Cau_Stat0)
GD32G553 User Manual Status register 0 (CAU_STAT0) 13.9.2. Address offset: 0x04 Reset value: 0x0000 0003 This register has to be accessed by word (32-bit) Reserved Reserved BUSY Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing.
Page 369: Data Output Register (Cau_Do)
GD32G553 User Manual is 0 and the input FIFO is not empty, when it is read, then the first data in the FIFO is popped out and returned. If the CAUEN is 1, the returned value is undefined. Once it is read, then the FIFO must be flushed.
Page 370: Interrupt Enable Register (Cau_Inten)
GD32G553 User Manual Reserved Reserved DMAOEN DMAIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN DMA output enable 0: DMA for OUT FIFO data is disabled 1: DMA for OUT FIFO data is enabled DMAIEN DMA input enable...
Page 371: Status Register 1 (Cau_Stat1)
GD32G553 User Manual Status register 1 (CAU_STAT1) 13.9.7. Address offset: 0x18 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit) Reserved Reserved OSTA ISTA Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. OSTA...
Page 372: Key Registers (Cau_Key0
GD32G553 User Manual 0: IN FIFO Interrupt not pending 1: IN FIFO Interrupt pending when CAUEN is 1 Key registers (CAU_KEY0..3(H/L)) 13.9.9. Address offset: 0x20 to 0x3C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0.
Page 373 GD32G553 User Manual KEY0L[15:0] CAU_KEY1H Address offset: 0x28 Reset value: 0x0000 0000 KEY1H[31:16] KEY1H[15:0] CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 KEY1L[31:16] KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0] CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000...
Page 374: Initial Vector Registers (Cau_Iv0
GD32G553 User Manual KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16] KEY3L[15:0] Bits Fields Descriptions KEY0...3(H/L) The key for DES, TDES, AES 31:0 Initial vector registers (CAU_IV0..1(H/L)) 13.9.10.
Page 375 GD32G553 User Manual CAU_IV0H Address offset: 0x40 Reset value: 0x0000 0000 IV0H[31:16] IV0H[15:0] CAU_IV0L Address offset: 0x44 Reset value: 0x0000 0000 IV0L[31:16] IV0L[15:0] CAU_IV1H Address offset: 0x48 Reset value: 0x0000 0000 IV1H[31:16] IV1H[15:0] CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000...
Page 376: Gcm Or Ccm Mode Context Switch Register X (Cau_Gcmccmctxsx) (X=0
GD32G553 User Manual Bits Fields Descriptions IV0...1(H/L) The initialization vector for DES, TDES, AES 31:0 GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) 13.9.11. (x=0..7) Address offset: 0x50 to 0x6C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 377: Trigonometric Math Unit (Tmu)
GD32G553 User Manual Trigonometric Math Unit (TMU) Overview 14.1. The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. The TMU can reduce the burden of CPU, and it is usually used in motor control, signal processing and many other applications.
Page 378: Function Overview
GD32G553 User Manual hyperbolic system, and each system supports rotation pattern and vectoring pattern. The Post-process module converts and scales the data (x ) and writes the processed results into TMU_ODATA register. The contents of the TMU_ODATA register are in the fixed point q1.31 / q1.15 format or IEEE754 32-bit single precision floating-point format.
Page 379: Floating-Point Data Format
GD32G553 User Manual in floating-point format (OFLTEN=1), the configuration of the OWIDTH bit is invalid. Each mode requires a different number of output data (for example, mode 0 has two output datas and mode 8 only has one), and can be configured via the ONUM bit of the TMU_CS register.
Page 380: Mode Configuration
GD32G553 User Manual De-Normalized Numbers: A de-normalized operand (E=0, M!=0) input is treated as zero (E=0, M=0) by all TMU operations. Not a Number (NaN): An NaN operand (E=max, M!=0) input is treated as Infinity (E=max, M=0) for all operations.
Page 381: Table 14-5. Mode 0 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual Table 14-5. Mode 0 description, when IFLTEN = 1 and OFLTEN = 1 Parameter Range Description The angle θ is in radians and overflow when exceed θ ∈(-2^24,2^24) First input data π the range. m∈(-∞,+∞) Second input data Overflow when m is too big for floating-point number m* cos ( θ...
Page 382: Table 14-7. Mode 1 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual parameter m . Modulus 100 is divided by 128 : =0.78125 . 0.78125 is 0x6400 in q1.15 format. TMU_IDATA. 3. The first input data 0x 4000 is written into 4. The second input data 0x 6400 TMU_IDATA. Then the TMU calculation is written into starts..
Page 383 GD32G553 User Manual Parameter Range Description must be applied in software to convert it to the range [-1,1), and then it is written to TMU_IDATA register according to the format of q1.31, q1.15 or float. m* sin ( θ ) ∈[-1,1)
Page 384: Table 14-9. Mode 2 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual Table 14-9. Mode 2 description, when IFLTEN = 1 and OFLTEN = 1 Parameter Range Description First input data 2^-24<|y/x|<2^24 Overflow when exceed the range. Second input data Angle, [-1,1) corresponding [-π, π). The output θ∈[-1,1) First output data data is multiplied by π...
Page 385: Table 14-11. Mode 3 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual The scaling 128 is used for the input datas and the modulus in this example. Of course, other scaling, such as 81, can also be used. Mode 3: modulus=√x Mode 3 calculates the modulus √x of a vector (x,y). This mode takes two input datas and generates two ouput datas.
Page 386: Table 14-13. Mode 4 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual (0.0390625,0.625). The q1.15 format is (0x0500,0x5000). 2. The first input data 0x0500 is written into TMU_IDATA. 3. The second input data 0x5000 is written into TMU_IDATA. Then the TMU calculation starts. 4. When the ENDF flag is set to 1, reading the TMU_ODATA register can get the first output data modulus m, and reading the TMU_ODATA register again can get the second output data θ.
Page 387: Table 14-15. Mode 5 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual For example, calculating tan ( 100 ) . When the IFLTEN and OFLTEN bits are reset, and IWIDTH and OWIDTH bits are set, the input and output are q1.15 format. The steps to calculate the function are as follows: 1.
Page 388: The Scaling Factor
GD32G553 User Manual For example, calculating cosh (1.0). When the IFLTEN and OFLTEN bits are reset, and IWIDTH and OWIDTH bits are set, the input and output are q1.15 format. The steps to calculate the function are as follows: 1. Software processes the input parameter 1.0. 1.0 is divided by 2 (f=3 b001).
Page 389: Table 14-19. Mode 7 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual Note: When IFLTEN = 0 or OFLTEN = 0, the scaling factor FACTOR[2:0] must be 3’b001. For example, calculating sinh (1.0). When the IFLTEN and OFLTEN bits are reset, and IWIDTH and OWIDTH bits are set, the input and output are q1.15 format. The steps to calculate the function are as follows: 1.
Page 390: Table 14-21. Mode 8 Description, When Iflten = 1 And Oflten = 1
GD32G553 User Manual IWIDTH and OWIDTH bits are set, the input and output are q1.15 format. The steps to calculate the function are as follows: 1. Software processes the input parameter 0.5. 0.5 is divided by 2 (f=3 b001). The result is 0.25 and the q1.15 format is 0x2000.
Page 391: Table 14-23. Recommended Scaling Factors In Mode 8
GD32G553 User Manual 1. Software processes the input parameter 8. 8 is divided by 16 (f=3 b100). The result is 0.5 and the q1.15 format is 0x4000. 2. The scaling factor f=3 b100 is written into FACTOR[2:0] bit-field in TMU_CS register.
Page 392: Tmu Operation Pending
GD32G553 User Manual Note: When IFLTEN = 0 or OFLTEN = 0, the scaling factor FACTOR[2:0] needs to be configured. For example, calculating √2. When the IFLTEN and OFLTEN bits are reset, and IWIDTH and OWIDTH bits are set, the input and output are q1.15 format. The steps to calculate the function are as follows: 1.
Page 393: Zero-Overhead Mode
GD32G553 User Manual Zero-overhead mode 14.4.5. After a TMU operation starts, the output data register can be read directly. And the bus will automatically insert the waiting cycle before the result is returned. The following steps can be followed: 1. Configure TMU_CS register as needed.
Page 394 GD32G553 User Manual Bits Fields Descriptions ENDF End of TMU operation flag 0: No TMU operation or TMU operation is ongoing 1: TMU operation ends and the output data has been written into TMU_ODATA register. This bit is set by hardware when TMU operation ends and the output data has been written into TMU_ODATA register.
Page 395 GD32G553 User Manual Note: This bit-field takes effect if the output data is in the fixed point format (OFLTEN=0). INUM The number of times that the TMU_IDATA needs to be written 0: One 32-bit write operation. To start a new TMU operation, one 32-bit input data must be writen into TMU_IDATA register.
Page 396: Input Data Register (Tmu_Idata)
GD32G553 User Manual … 110: 2 111: 2 When the actual input parameter exceeds the specified the input data range [-1,1), FACTOR[2:0] it is need to be divide by 2 and the output data is need to be multiplied by...
Page 397: Output Data Register (Tmu_Odata)
GD32G553 User Manual IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] The input data Table 14-1. Input data The input data is written into this register. For details, refer to configuration. Note: 1. When no TMU operation is is ongoing and the required number of arguments has been written, a new operation will be started automatically.
Page 398: Fast Fourier Transform (Fft)
GD32G553 User Manual Fast Fourier Transform (FFT) 15.1. Overview The Fast Fourier Transform (FFT) is an efficient computation of the Discrete Fourier Transform (DFT). The module supports CPU to offload FFT operations. Compared to a software implementation, it can accelerate calculations and time critical tasks. The module supports 6 configruation FFT point number up to 1024, and input and output data should be IEEE-754 single precision float point complex number.
Page 399: Data Format
GD32G553 User Manual register. The module is based on redix-2 FFT algorithm. The input data including real, image and window data in the format of IEEE754 single precision float point is loaded from memory, and after window function operation and input bits reverse operation they are written into internal SRAM.
Page 400: Radix-2 Fft
GD32G553 User Manual 15.5. Radix-2 FFT The FFT module uses the DIT(Decimation in Time) Radix-2 algorithms, which relies on the recursive decomposition of an N point transform into two (N/2) point transforms. For illustrative purposes, the 8 points (N=8) decimation in time algorithm is shown in the...
Page 401: Ifft Mode
GD32G553 User Manual Figure 15-3. 8 points DIT FFT flow digram ′ = �� + �� = �� ( �� ) + �� ( �� ) + ��[�� ( �� ) + �� ( �� ) ] ′ = �� − �� = �� ( �� ) − �� ( �� ) + ��[�� ( �� ) − �� ( �� ) ] 2��...
Page 402: Operation Guide
GD32G553 User Manual 15.10. Operation guide This section describes the advised operation guide for FFT. 1. Configure the FFT_IMSADDR to set the FFT image start address, if necessary, that is, the image data is not zero. 2. Configure the FFT_RESADDR to set the FFT real start address.
Page 403: Fft Interrupts
GD32G553 User Manual FFT interrupts 15.11. The interrupt can be produced on one of the flags:  FFT calculation completion flag  Transfer access error interrupt flag These interrupts of FFT are mapped into the same interrupt vector IRQ96.
Page 404: Register Definition
GD32G553 User Manual 15.12. Register definition FFT start address: 0x4002 5000 Control and status register (FFT_CSR) 15.12.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) DMABSY CCIE TAEIF TAEIE Reserved rc_w1 rc_w1...
Page 405 GD32G553 User Manual 01: Image input is 0 10: Image input is the opposite number of image data from FFT_IMSADDR DOWNSAMP[3:0] Input data down sample selection 12:9 0000: Down sample 1 0001: Down sample 2 0010: Down sample 3 0011: Down sample 4...
Page 406: Real Start Address Register(Fft_Resaddr)
GD32G553 User Manual 0: Disable FFT 1: Enable FFT Real start address register(FFT_RESADDR) 15.12.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). RESADDR[31:16] RESADDR[15:0] Bits Fields Descriptions 31:0 RESADDR[31:0] FFT real start address The address must be aligned to 32-bit.
Page 407: Output Start Address Register (Fft_Osaddr)
GD32G553 User Manual This register has to be accessed by word (32-bit). FFT_WSADDR[31:16] FFT_WSADDR[15:0] Bits Fields Descriptions 31:0 FFT_WSADDR[31:0] FFT window start address The address must be aligned to 32-bit. These bits can not be written when FFTEN in the FFT_CSR register is ‘1’.
Page 408 GD32G553 User Manual Bits Fields Descriptions 31:16 INDEX[15:0] The index of DMA loop buffer The index can not more than LENGTH[15:0] and it ranges from 0 to LENGTH[15:0]. Add 1 at each end and clear 0 when increasing to LENGTH[15:0].
Page 409: Debug (Dbg)
GD32G553 User Manual Debug (DBG) 16.1. Overview The GD32G553 series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSight™ module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Cortex -M33.
Page 410: Jtag
GD32G553 User Manual Table 16-1. Pin assignment Debug interface PA15 JTDI PA14 JTCK / SWCLK PA13 JTMS / SWDIO JTDO NJTRST By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions (NJTRST tied to 1 by hardware).
Page 411: Table 16-2. Otp Jtag Bytes
GD32G553 User Manual Secure JTAG Secure JTAG only supports JTAG but not SW OTP configuration: OTP related bits: SWEN, NDBG[1:0], DPx[31:0](x=0,1) Table 16-2. OTP JTAG bytes Address Name abbreviations Description secure JTAG password 0 0x1fff f000 DP0[31:0] Factor value: 0xFFFFFFFF...
Page 412: Debug Reset
GD32G553 User Manual 2 Any wrong input sequence occurrs, a power reset is required to re-decrypt. Get written value and JTAG status: Get the written value and JTAG status via JTAG: Write 5’b11000 to IR, read value from DR: It can be judged whether the read IR value is the written 5’b11000...
Page 413: Debug Support For Timer, I2C, Wwdgt, Fwdgt, Rtc, Can, Lptimer And Hrtimer
GD32G553 User Manual When SLP_HOLD bit in DBG control register (DBG_CTL0) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT, RTC, CAN, LPTIMER 16.3.2.
Page 414: Register Definition
GD32G553 User Manual 16.4. Register definition DBG base address: 0xE004 4000 ID code register (DBG_ID) 16.4.1. Address offset: 0x00 Reset value: 0xXXXX XXXX This register attribute is read-only. This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits...
Page 415: Control Register1 (Dbg_Ctl1)
GD32G553 User Manual STB_HOLD Standby mode hold bit This bit is set and reset by software. 0: No effect 1: In the standby mode, all active clocks continue to run, the debugger can debug in standby mode. DSLP_HOLD Deep-sleep mode hold bit This bit is set and reset by software.
Page 416 GD32G553 User Manual This bit is set and reset by software. 0: No effect 1: Hold the I2C2 SMBUS timeout for debug when core is halted. I2C1_HOLD I2C1 hold bit This bit is set and reset by software. 0: No effect 1: Hold the I2C1 SMBUS timeout for debug when core is halted.
Page 417: Control Register2 (Dbg_Ctl2)
GD32G553 User Manual This bit is set and reset by software. 0: No effect 1: Hold the TIMER3 counter clock for debug when core is halted. TIMER2_HOLD TIMER2 hold bit This bit is set and reset by software. 0: No effect 1: Hold the TIMER2 counter clock for debug when core is halted.
Page 418 GD32G553 User Manual 0: No effect 1: Hold the TIMER16 counter clock for debug when core is halted. TIMER15_HOLD TIMER15 hold bit This bit is set and reset by software. 0: No effect 1: Hold the TIMER15 counter clock for debug when core is halted.
Page 419: Analog-To-Digital Converter (Adc)
GD32G553 User Manual Analog-to-digital converter (ADC) 17.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip. ADC0 has 14 external channels, 5 internal channels (temperature sensor, the battery voltage, DAC0_OUT0, DAC0_OUT1, V inputs channel), ADC1 has 16 external...
Page 420: Pins And Internal Signals
GD32G553 User Manual Continuous operation mode converts selected inputs continuously. – Discontinuous operation mode. – SYNC mode (the device with two or three ADCs). –  Conversion result threshold monitor function: analog watchdog.  Interrupt generation at the end of routine sequence conversions, in case of analog watchdog event and overflow event.
Page 421: Function Overview
GD32G553 User Manual 17.4. Function overview Figure 17-1. ADC module block diagram Analog watch dog watchdog Trig select event ETSRC 0/1/2 0/1/2 Interrupt Routine sequence Channel Management ADC_IN0 ADC_IN1 GPIO Over Routine data registers ADC_IN17 SAR ADC （32 bits） sampler...
Page 422: Dual Clock Domain Architecture
GD32G553 User Manual Set CLB=1. Wait until CLB=0. Dual clock domain architecture 17.4.2. The CK_ADC clock provided by the clock controller is synchronous with the AHB clock. In this mode, ADCSCK[3:0] in ADC_SYNCCTL should be set different from 0000.The divide factor can be 2, 4, 6, 8, 10, 12, 14,16.
Page 423: Routine Sequence
GD32G553 User Manual PD10 PD10 PD10 PD11 PD10 PD11 PD11 PD12 PD11 PD12 PD12 PD13 PD12 PD13 PB12 PD13 PD14 PD13 PD14 PB12 PD14 PD14 PE11 PE10 PB11 PE10 PE11 PE10 PB11 PB11 PB15 PE12 PE11 PE10 PE11 PB12 PB11...
Page 424: Operation Modes
GD32G553 User Manual Operation modes 17.4.6. Single operation mode In the single operation mode, the ADC performs conversion on the channel specified in the RSQ0[4:0] bits of ADC_RSQ8 register at a routine trigger. When the ADCON has been set high, the ADC samples and converts a single channel, once the corresponding software trigger or TRIGSEL trigger is active.
Page 425: Figure 17-4. Scan Operation Mode, Continuous Disable
GD32G553 User Manual Software procedure for continuous operation mode on a routine channel: Set the CTN bit in the ADC_CTL1 register. Configure RSQ0 with the analog channel number. Configure ADC_RSQx register. Configure ETMRC[1:0] bits in the ADC_CTL1 register if in need.
Page 426: Figure 17-5. Scan Operation Mode, Continuous Enable
GD32G553 User Manual Prepare the DMA module to transfer data from the ADC_RDATA (refer to the spec of the DMA module). Set the SWRCST bit, or generate an TRIGSEL trigger for the routine sequence. Wait the EOC flag to be set.
Page 427: Conversion Result Threshold Monitor Function
GD32G553 User Manual Conversion result threshold monitor function 17.4.7. Analog watchdog 0 The analog watchdog 0 is enabled when the RWD0EN bit in the ADC_CTL0 register is set for routine sequence. This function is used to monitor whether the conversion result exceeds the set thresholds, and when the analog voltage converted by the ADC is below a low threshold or above a high threshold, the WDE0 bit in ADC_STAT register will be set.
Page 428: Sample Time Configuration
GD32G553 User Manual Figure 17-8. 6-bit data storage mode Routine channel data DAL=0 Routine channel data DAL=1 NOTE: When OVSEN bit in the ADC_OVSAMPCTL register is set, the DAL bit value in the ADC_CTL1 register is ignored and the ADC only support LSB storage mode.
Page 429: Adc Internal Channels
GD32G553 User Manual been read out. The ROVF bit of the ADC_STAT is set. Overflow interrupt is generated if the ROVFIE bit in the ADC_CTL0 is set. It is recommended to reinitialize the DMA module to recover the ADC from ROVF state. To ensure the routine converted data are transferred correctly, the internal state machine is reset.
Page 430: Battery Voltage Monitoring
GD32G553 User Manual Read the temperature data(V ) in the ADC data register, and get the temperature temperature with the following equation. Temperature (°C) = {(V – V (digit)) / Avg_Slope} + 25. temperature value at 25°C, the typical value please refer to the datasheet.
Page 431: Programmable Resolution (Dres)
GD32G553 User Manual bits and SYNCDDM bit must be cleared to 0. If DMA and HPDF work in parallel,only DMA takes effect. The ADC transfers 16 least significant bits of the routine data register data to the HPDF, which in turns will reset the EOC flag once the transfer is complete. As shown in Figure 17-9.
Page 432: Gain Mode
GD32G553 User Manual bit right shifting up to 11-bit. It is configured through the OVSS[3:0] bits in the ADC_OVSAMPCTL register. The summation unit can produce up to 22 bits (1024 x 12bit), which is first shifted right. Then store the data into register.
Page 433: Adc Sync Mode
GD32G553 User Manual Figure 17-11. ADC convertsion signal in continuous operation mode 17.5. ADC sync mode In devices with more than one ADC, the ADC sync mode can be used. In ADC sync mode, the conversion starts alternately or simultaneously triggered by ADC0/ADC1/ADC2, according to the sync mode configurated by the SYNCM[4:0] bits in ADC_SYNCCTL register.
Page 434: Free Mode
GD32G553 User Manual The ADC sync scheme is shown in Figure 17-12. ADC sync block diagram Figure 17-12. ADC sync block diagram Routine Routine data registers （32 bits） sequence ADC2 (slave) Routine Routine data registers （32 bits） sequence ADC1 (slave)
Page 435: Follow-Up Mode
GD32G553 User Manual mode is shown in the Figure 17-13. Routine parallel mode on 16 channels . Figure 17-13. Routine parallel mode on 16 channels · · · · · · ADC0 CH14 CH15 · · · ADC1 · · ·...
Page 436: Use Dma In Adc Sync Mode
GD32G553 User Manual Figure 17-14. Follow-up mode on 1 channel in continuous operation mode Note: Do not convert the same channel on two ADCs at a given time (no overlapping sampling times for the two ADCs when converting the same channel).
Page 437: Adc Interrupts
GD32G553 User Manual two data, which are selected from the routine data of the ADCs in turn. For every request, the source address of the DMA channel should be fixed to the ADC_SYNCDATA register, while the content of the ADC_SYNCDATA changes to the data that is to be transferred. When ADC0 and ADC1 works in SYNC mode, the transfer data are always {ADC1_RDATA[15:0], ADC0_RDATA[15:0]}.
Page 438: Register Definition
GD32G553 User Manual 17.7. Register definition ADC0 base address: 0x5000 0000 ADC1 base address: 0x5000 0400 ADC2 base address: 0x5000 0800 ADC3 base address: 0x5000 0C00 Status register (ADC_STAT) 17.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 439: Control Register 0 (Adc_Ctl0)
GD32G553 User Manual STRC Start flag of routine sequence 0: Conversion is not started 1: Conversion is started Set by hardware when routine sequence conversion starts. Cleared by software writing 0 to it. Reserved Must be kept at reset value.
Page 440 GD32G553 User Manual 1: ROVF interrupt enable 25:24 DRES[1:0] ADC data resolution 00: 12bit 01: 10bit 10: 8bit 11: 6bit RWD0EN Routine channel analog watchdog 0 enable 0: Routine channel analog watchdog 0 disable 1: Routine channel analog watchdog 0 enable...
Page 441: Control Register 1 (Adc_Ctl1)
GD32G553 User Manual 00110: ADC channel 6 00111: ADC channel 7 01000: ADC channel 8 01001: ADC channel 9 01010: ADC channel 10 01011: ADC channel 11 01100: ADC channel 12 01101: ADC channel 13 01110: ADC channel 14 01111: ADC channel 15...
Page 442 GD32G553 User Manual 0: high-precision temperature sensor Channel disable 1: high-precision temperature sensor Channel enable SWRCST Software start on routine channel. Setting 1 on this bit starts a conversion of a sequence of routine channels. It is set by software and cleared by software or by hardware immediately after the conversion starts.
Page 443 GD32G553 User Manual HPDFCFG HPDF mode configuration To enable the HPDF mode, this bit is set and cleared by software. It is only valid when DMA=0. 0: HPDF mode disabled 1: HPDF mode enabled Data alignment 0: LSB alignment 1: MSB alignment...
Page 444: Watchdog High Threshold Register0 (Adc_Wdht0)
GD32G553 User Manual Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC will be wake up when this bit is changed from low to high and take a stabilization time. For power saving, when this bit is reset, the analog submodule will be put into power down mode.
Page 445: Routine Sequence Register 0 (Adc_Rsq0)
GD32G553 User Manual Low threshold for analog watchdog 0 21:0 WDLT0[21:0] These bits define the low threshold for the analog watchdog. Routine sequence register 0 (ADC_RSQ0) 17.7.6. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 446: Routine Sequence Register 2 (Adc_Rsq2)
GD32G553 User Manual Refer to RSMP0[9:0] description. 20:16 RSQ14[4:0] refer to RSQ0[4:0] description Reserved Must be kept at reset value. 14:5 RSMP13[9:0] Routine channel sample time Refer to RSMP0[9:0] description. RSQ13[4:0] refer to RSQ0[4:0] description Routine sequence register 2 (ADC_RSQ2) 17.7.8.
Page 447: Routine Sequence Register 4 (Adc_Rsq4)
GD32G553 User Manual Reserved RSMP9[9:0] RSQ9[4:0] Bits Fields Descriptions Reserved Must be kept at reset value. 30:21 RSMP10[9:0] Routine channel sample time Refer to RSMP0[9:0] description. 20:16 RSQ10[4:0] refer to RSQ0[4:0] description Reserved Must be kept at reset value. 14:5...
Page 448: Routine Sequence Register 5 (Adc_Rsq5)
GD32G553 User Manual Routine sequence register 5 (ADC_RSQ5) 17.7.11. Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RSMP6[9:0] RSQ6[4:0] Reserved RSMP5[9:0] RSQ5[4:0] Bits Fields Descriptions Reserved Must be kept at reset value.
Page 449: Routine Sequence Register 7 (Adc_Rsq7)
GD32G553 User Manual 20:16 RSQ4[4:0] refer to RSQ0[4:0] description Reserved Must be kept at reset value. 14:5 RSMP3[9:0] Routine channel sample time Refer to RSMP0[9:0] description. RSQ3[4:0] refer to RSQ0[4:0] description Routine sequence register 7 (ADC_RSQ7) 17.7.13. Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 450: Routine Data Register (Adc_Rdata)
GD32G553 User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. 14:5 RSMP0[9:0] Routine channel sample time ADC sample time is RSMP0[9:0] + 2.5 cycles. For example, RSMP0[9:0] = 100, the sample time is 102.5 cycles. RSMP0[9:0] max is 638, all other values are reserved.
Page 451 GD32G553 User Manual 31:26 Reserved Must be kept at reset value. 25:16 OVSR[9:0] Oversampling ratio This bit filed defines the number of oversampling ratio. 10’d0: 1x (no oversampling) 10’d1: 2x 10’d2: 3x …… 10’d1023:1024x Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress).
Page 452: Watchdog 1 Channel Selection Register (Adc_Wd1Sr)
GD32G553 User Manual that no conversion is in progress). Watchdog 1 Channel Selection Register (ADC_WD1SR) 17.7.17. Address offset: 0xA0 Reset value: 0x00000000 This register has to be accessed by word (32-bit). Reserved AWD1CS[21:16] AWD1CS[15:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value.
Page 453: Watchdog High Threshold Register1 (Adc_Wdht1)
GD32G553 User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:0 AWD2CS[21:0] Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2.
Page 454: Watchdog High Threshold Register2 (Adc_Wdht2)
GD32G553 User Manual WDLT1[15:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. Low threshold for analog watchdog 1 21:0 WDLT1[23:0] These bits define the high threshold for the analog watchdog 1. Note: Software is allowed to write these bits only when the ADC is disabled (ADCON =0).
Page 455: Differential Mode Control Register (Adc_Difctl)
GD32G553 User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. Low threshold for analog watchdog 2 21:0 WDLT2[21:0] These bits define the high threshold for the analog watchdog 2. Note: Software is allowed to write these bits only when the ADC is disabled (ADCON =0).
Page 456: Summary Status Register (Adc_Sstat)
GD32G553 User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value 13:0 GAIN[13:0] Gain factor These bits can be set or cleared by software to program the gain factor. The programmable range of GAIN is 0 to 16383, and the actual gain calculation factor (GAIN / 4096) is 0 to 3.999756.
Page 457: Sync Control Register (Adc_Syncctl)
GD32G553 User Manual ADC3_EOC This bit is the mirror image of the EOC bit of ADC3 ADC3_WDE2 This bit is the mirror image of the WDE2 bit of ADC3 ADC3_WDE1 This bit is the mirror image of the WDE1 bit of ADC3...
Page 458 GD32G553 User Manual This register has to be accessed by word (32-bit). Reserved ADCCK[3:0] ADCSCK[3:0] SYNCDMA[1:0] SYNCDDM Reserved SYNCDLY[3:0] Reserved SYNCM[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 ADCCK[3:0] ADC clock prescaler. ADC Prescaler These bits are set and cleared by software to select the frequency of the ADC clock.
Page 459: Sync Routine Data Register (Adc_Syncdata)
GD32G553 User Manual 01: ADC sync DMA mode 0 10: ADC sync DMA mode 1 11: reserved SYNCDDM ADC sync DMA disable mode This bit configures the DMA disable mode for ADC sync mode 0: The DMA engine is disabled after the end of transfer signal from DMA controller is detected.
Page 460 GD32G553 User Manual SYNCDATA1[31:16] Routine data 1 in ADC sync mode 31:16 Routine data 0 in ADC sync mode 15:0 SYNCDATA0[15:0]...
Page 461: Digital-To-Analog Converter (Dac)
GD32G553 User Manual Digital-to-analog converter (DAC) Overview 18.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers.
Page 462: Table 18-1. Dac I/O Description
GD32G553 User Manual Figure 18-1. DAC block diagram DAC control register DTSELx[1:0]/ SAWRSTTSELx[1:0] DACy_OUTx_ EXTRIG MODEx SWTRx OTVx DAC_CALR DACy_OUTx_ ST_EXTRIG SWSTTRx DAC_ENx Control logic buff Sample and keep Wave OUTx_DH OUTx_DO (optional) 12-bit 12-bit 12-bit 12-bit Table 18-1. DAC I/O description...
Page 463: Function Overview
GD32G553 User Manual Note: The GPIO pins should be configured to analog mode before enable the DAC module. Function overview 18.3. DAC enable 18.3.1. The DAC can be turned on by setting the DENx bit in the DAC_CTL0 register. A t...
Page 464: Dac Trigger
GD32G553 User Manual DHFMTx bit DATA written to Decimal DATA transfered to Output voltage DAC_OUTx_DH value DAC_OUTx_DO register register 0x800 -2048 0x000 DAC trigger 18.3.4. The DAC conversion can be triggered by software or rising edge of external trigger source.
Page 465: Dac Sawtooth Wave
GD32G553 User Manual width is less than 12, the noise signal equals to the LSB DWBWx bits of the LFSR register, while the MSB bits are masked. Figure 18-2. DAC LFSR algorithm Triangle noise mode: in this mode, a triangle signal is added to the OUTx_DH value, and then the result is stored into the DAC_OUTx_DO register.
Page 466: Figure 18-4. Dac Sawtooth Wave (Sawdirx = 1)
GD32G553 User Manual MSB of sawtooth counter value will be transferred to DAC_OUTx_DO register to output voltage. The sawtooth counter steps up/down(resets) at each rising edge of step(reset) trigger signal, which are selected by SAWRSTTSELx and SAWSTEPTSELx bits in DAC_SAWMDR register, respectively.
Page 467: Dac Output Voltage
GD32G553 User Manual Figure 18-5. DAC sawtooth wave (SAWDIRx = 0) SAWINITx[11:0] SAWSTEPx[11:0] Step trigger Reset trigger Note: The interval between two triggers (step and reset) of sawtooth wave mode output cannot be less than 1 hclk cycle or 1 pclk cycle.
Page 468: Dac Reset Persist Mode
GD32G553 User Manual to realize driving two DAC units at the same time. When using DMA function, please ensure both DTENx bits be set, DTSEL0/DTSEL1 bits be same to guarantee the simultaneous trigger. And any DDMAENx bit in one DAC setting to enable DMA request.
Page 469: Dac Output Buffer Calibration
GD32G553 User Manual DAC output buffer calibration 18.3.12. The output voltage may be offset when DAC use buffer, so it is necessary to compensate output voltage. The DAC calibration transfer function is: =(D/2 N−1 )*G*V (18-2) REFP Where N is the significant digit of the DAC, D is the digital input of the DAC, and G is the gain, is the positive reference voltage of the DAC, V is the offset voltage.
Page 470: Dac Modes
GD32G553 User Manual DAC modes 18.3.13. DAC two units can be set to normal mode or sample and keep mode. The DAC out can be connected to I/O pin or other peripherals. Normal mode When the MODEx[2] bit in the DAC_MDCR register is 0, DAC is in normal mode.
Page 471: Time Calculation
GD32G553 User Manual SAWRSTTSELx and DTSELx (x= 0,1) should keep same. Time calculation The calculation of the time for the three stages above are based on LXTAL/IRC32K clock periods. To configure enough sample and refresh time, refer to the following formula: Table 18-7.
Page 472: Dac Low-Power Modes
GD32G553 User Manual DAC low-power modes 18.3.14. Sleep mode In Sleep mode, DAC can work normally, and can be used with DMA. Deep-sleep mode In Deep-sleep mode, if sample and keep mode is enabled before entering Deep-sleep mode, DAC can still hold the static output, otherwise DAC stops working.
Page 473: Register Definition
GD32G553 User Manual Register definition 18.4. DAC0 base address: 0x5000 1000 DAC1 base address: 0x5000 1400 DAC2 base address: 0x5000 1800 DAC3 base address: 0x5000 1C00 DACx control register 0 (DAC_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 474 GD32G553 User Manual triangle is ((2 << (n-1)) - 1) in triangle noise mode, where n is the bit width of wave. 0000: The bit width of the wave signal is 1 0001: The bit width of the wave signal is 2...
Page 475 GD32G553 User Manual 1: DACx_OUT0 calibration mode enabled CALEN0 can be written to 1 only when DEN0 is 0. DDUDRIE0 DACx_OUT0 DMA underrun interrupt enable 0: DACx_OUT0 DMA underrun interrupt disabled 1: DACx_OUT0 DMA underrun interrupt enabled DDMAEN0 DACx_OUT0 DMA enable...
Page 476: Dacx Software Trigger Register (Dac_Swt)
GD32G553 User Manual 1: DACx_OUT0 trigger enabled DEN0 DACx_OUT0 enable 0: DACx_OUT0 disabled 1: DACx_OUT0 enabled DACx software trigger register (DAC_SWT) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved SWSTTR1 SWSTTR0...
Page 477: Dacx_Out0 12-Bit Right-Aligned Data Holding Register (Dac_Out0_R12Dh)
GD32G553 User Manual DACx_OUT0 12-bit right-aligned data holding register 18.4.3. (DAC_OUT0_R12DH) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value.
Page 478: Dacx_Out0 8-Bit Right-Aligned Data Holding Register (Dac_Out0_R8Dh)
GD32G553 User Manual DACx_OUT0 8-bit right-aligned data holding register (DAC_OUT0_R8DH) 18.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 479: Dacx_Out1 8-Bit Right-Aligned Data Holding Register (Dac_Out1_R8Dh)
GD32G553 User Manual This register has to be accessed by word(32-bit). Reserved OUT1_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 OUT1_DH[11:0] DACx_OUT1 12-bit left-aligned data. These bits specify the data that is to be converted by DACx_OUT1.
Page 480: Dacx Concurrent Mode 12-Bit Left-Aligned Data Holding Register (Dacc_L12Dh)
GD32G553 User Manual Reserved OUT0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:16 OUT1_DH[11:0] DACx_OUT1 12-bit right-aligned data These bits specify the data that is to be converted by DACx_OUT1. 15:12 Reserved Must be kept at reset value.
Page 481: Dacx_Out0 Data Output Register (Dac_Out0_Do)
GD32G553 User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved OUT1_DH [7:0] OUT0_DH [7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:8 OUT1_DH[7:0] DACx_OUT1 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT1.
Page 482: Dacx Status Register 0 (Dac_Stat0)
GD32G553 User Manual This register has to be accessed by word(32-bit). Reserved Reserved OUT1_DO [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT1_DO [11:0] DACx_OUT1 data output These bits, which are read only, storage the data that is being converted by DACx_OUT1.
Page 483: Dacx Calibration Register (Dac_Calr)
GD32G553 User Manual BWT0 DAC_OUT0 TSAMP0[9:0] writing busy flag. This bit is set by the system when the sample and keep mode is enabled. When the TSAMP0[9:0] is writing, this bit is set. This bit is cleared by hardware when the write operation is complete.
Page 484 GD32G553 User Manual Reserved DHFMT1 Reserved MODE1[2:0] Reserved DHFMT0 Reserved MODE0[2:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. DHFMT1 DACx_OUT1 data format written in data holding register. 0: Written data is handled as unsigned format. 1: Written data is handled as signed format (2’s complement).
Page 485: Dacx Sample And Keep Sample Time Register 0 (Dac_Skstr0)
GD32G553 User Manual 001: Buffer is enabled and DACx_OUT0 is connected to other peripherals and to I/O pin. 010: Buffer is disabled and DACx_OUT0 is connected to I/O pin. 011: Buffer is disabled and DACx_OUT0 is connected to other peripherals.
Page 486: Dacx Sample And Keep Keep Time Register (Dacx_Skktr)
GD32G553 User Manual Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TSAMP1[9:0] DACx_OUT1 sample time. DACx sample and keep keep time register (DACx_SKKTR) 18.4.19. Address offset: 0x48 Reset value: 0x0001 0001 This register has to be accessed by word(32-bit).
Page 487: Dacx_Out0 Sawtooth Register (Dac_Out0_Saw)
GD32G553 User Manual TREF0[7: 0] DACx_OUT refresh time (only available in sample and keep mode). DACx_OUT0 sawtooth register (DAC_OUT0_SAW) 18.4.21. Address offset: 0x58 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). SAWSTEP0[15:0] Reserved SAWDIR0 SAWINIT0[11:0] Bits...
Page 488: Dacx Sawtooth Mode Register (Dacx_Sawmdr)
GD32G553 User Manual SAWDIR1 DACx_OUT1 sawtooth step direction. This bit is written by software to select the direction of sawtooth step. 0: Step-down 1: Step-up 11:0 SAWINIT1[11:0] DACx_OUT1 sawtooth initial value. DACx sawtooth mode register (DACx_SAWMDR) 18.4.23. Address offset: 0x60 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 489 GD32G553 User Manual All other values: reserved.
Page 490: Comparator (Cmp)
GD32G553 User Manual Comparator (CMP) Overview 19.1. The general purpose CMP can work either standalone (all terminal are available on I/Os) or together with the timers. It can be used to wake up the MCU from low-power mode by an analog signal, provide a trigger source when an analog signal is in a certain condition, achieve some current control by working together with a PWM output of a timer and the DAC.
Page 491: Cmp Clock
GD32G553 User Manual Figure 19-1. CMP block diagram 0000 0001 0010 0011 0100 CMP0PSEL 0101 0110 0111 CMP0BLK[3:0] Polarity Selection CMP0PL Squential logic CMP0MSEL[2:0] Note: is 1.2V. REFINT CMPx(x=1,2..7) as the same CMP0, CMPxPSEL, CMPxBLK, CMPxMSEL etc. refer to table Table 19-1.
Page 492 GD32G553 User Manual CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 inputs connected to I/Os inverting PB10 PD10 PD15 inputs PD13 PB15 PB12 connected to I/Os REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT REFINT...
Page 493: Cmp Hysteresis
GD32G553 User Manual CMP hysteresis 19.3.3. In order to avoid spurious output transitions that caused by the noise signal, a programmable hysteresis is designed to force the hysteresis value by configuring CMPx_CS register. This function could be shut down if it is unnecessary.
Page 494: Cmp Voltage Scaler Function
GD32G553 User Manual Figure 19-3. The CMP outputs signal blanking CMPx_IM CMPx_IP Blanking signal CMP outputs raw singal CMP outputs final singal CMP voltage scaler function 19.3.6. The voltage scaler function can provide selectable 1 / 4, 1 / 2, 3 / 4 reference voltage for CMP input.
Page 495: Register Definition
GD32G553 User Manual 19.4. Register definition CMP base address: 0x4001 7C00 CMP status register (CMP_STAT) 19.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CMP7IF CMP6IF CMP5IF CMP4IF CMP3IF CMP2IF CMP1IF...
Page 496 GD32G553 User Manual 1: CMP3 output interrupt Set by hardware when the CMP3 output is set. Cleared by software writing 1 to CMP3IC bit in the CMP_IFC register. CMP2IF CMP2 interrupt flag 0: No CMP2 output interrupt 1: CMP2 output interrupt Set by hardware when the CMP2 output is set.
Page 497: Cmp Interrupt Flag Clear Register (Cmp_Ifc)
GD32G553 User Manual This bit is a copy of CMP2 output state, which is read only. 0: Non-inverting input below inverting input and the output is low 1: Non-inverting input above inverting input and the output is high CMP1O CMP1 output state This bit is a copy of CMP1 output state, which is read only.
Page 498: Cmp0 Control/Status Register (Cmp0_Cs)
GD32G553 User Manual 0: Not clear CMP3 interrupt flag 1: Clear CMP3 interrupt flag CMP2IC CMP2 interrupt flag clear 0: Not clear CMP2 interrupt flag 1: Clear CMP2 interrupt flag CMP1IC CMP1 interrupt flag clear 0: Not clear CMP1 interrupt flag...
Page 499 GD32G553 User Manual 0100: Select TIMER7_CH2 output compare signal as blanking source 0101: Select TIMER19_CH2 output compare signal as blanking source 0110: Select TIMER14_CH0 output compare signal as blanking source 0111: Select TIMER3_CH2 output compare signal as blanking source All other values: reserved.
Page 500: Cmp1 Control/Status Register (Cmp1_Cs)
GD32G553 User Manual 1: Enabled Reserved Must be kept at reset value. CMP0PL Polarity of CMP0 output This bit is used to select the polarity of CMP0 output. 0: Output is not inverted 1: Output is inverted CMP0SEN Voltage scaler enable bit This bit is set and cleared by software.
Page 501 GD32G553 User Manual 30:28 Reserved Must be kept at reset value. 27:24 CMP1BLK[3:0] CMP1 output blanking source This bit is used to select which timer output controls the comparator output blanking. 0000: No blanking 0001: Select TIMER0_CH2 output compare signal as blanking source...
Page 502: Cmp2 Control/Status Register (Cmp2_Cs)
GD32G553 User Manual CMP1RSTMD CMP1 reset mode. This bit can only be reset by power on reset 0: Normal mode. All resets will reset CMP1 and its associated registers 1: Reset persist mode. CMP1 output will persist through all resets except for power-...
Page 503 GD32G553 User Manual Bits Fields Descriptions CMP2LK CMP2 lock This bit allows to have all control bits of CMP2 as read-only. It can only be set once by software and cleared by a system reset. 0: CMP2_CS bits are read-write...
Page 504: Cmp3 Control/Status Register (Cmp3_Cs)
GD32G553 User Manual 010: 20 mv 011: 30 mv 100: 40 mv 101: 50 mv 110: 60 mv 111: 70 mv CMP2RSTMD CMP2 reset mode. This bit can only be reset by power on reset 0: Normal mode. All resets will reset CMP2 and its associated registers 1: Reset persist mode.
Page 505 GD32G553 User Manual CMP3RST CMP3INT Reserved CMP3HST[2:0] Reserved CMP3PL CMP3SEN CMP3BEN CMP3EN Bits Fields Descriptions CMP3LK CMP3 lock This bit allows to have all control bits of CMP3 as read-only. It can only be set once by software and cleared by a system reset.
Page 506 GD32G553 User Manual 111: PB2 15:11 Reserved Must be kept at reset value. 10:8 CMP3HST[2:0] CMP3 hysteresis These bits are used to control the hysteresis level. 000: No hysteresis 001: 10 mv 010: 20 mv 011: 30 mv 100: 40 mv...
Page 507: Cmp4 Control/Status Register (Cmp4_Cs)
GD32G553 User Manual CMP4 control/status register (CMP4_CS) 19.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP4PS CMP4LK Reserved CMP4BLK[3:0] Reserved Reserved CMP4MSEL[2:0] CMP4RST CMP4INT Reserved CMP4HST[2:0] Reserved CMP4PL CMP4SEN CMP4BEN CMP4EN...
Page 508 GD32G553 User Manual of the CMP4. 000: V REFINT 001: V REFINT 010: V *3 / 4 REFINT 011: V REFINT 100: DAC3_OUT0 101: DAC0_OUT1 110: PB10 111: PD13 15:11 Reserved Must be kept at reset value. 10:8 CMP4HST[2:0] CMP4 hysteresis These bits are used to control the hysteresis level.
Page 509: Cmp5 Control/Status Register (Cmp5_Cs)
GD32G553 User Manual reset 1: Enable scaler resistor bridge CMP4EN CMP4 enable 0: CMP4 disabled 1: CMP4 enabled CMP5 control/status register (CMP5_CS) 19.4.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP5PS...
Page 510 GD32G553 User Manual This bit is used to select the source connected to the CMP5_IP input of the CMP5. 0: PB11 1: PD11 Reserved Must be kept at reset value. 18:16 CMP5MSEL[2:0] CMP5_IM internal input selection These bits are used to select the internal source connected to the CMP5_IM input of the CMP5.
Page 511: Cmp6 Control/Status Register (Cmp6_Cs)
GD32G553 User Manual This bit is set and cleared by software. This bit enables the outputs of the VREFINT divider, which is treated as the minus input of the comparator. 0: Disable bandgap scaler disable in case that CMP4SEN bit of CMP4_CS is also...
Page 512 GD32G553 User Manual 0101: Select TIMER19_CH2 output compare signal as blanking source 0110: Select TIMER14_CH0 output compare signal as blanking source 0111: Select TIMER3_CH2 output compare signal as blanking source All other values: reserved. 23:21 Reserved Must be kept at reset value.
Page 513: Cmp7 Control/Status Register (Cmp7_Cs)
GD32G553 User Manual Reserved Must be kept at reset value. CMP6PL Polarity of CMP6 output This bit is used to select the polarity of CMP6 output. 0: Output is not inverted 1: Output is inverted CMP6SEN Voltage scaler enable bit This bit is set and cleared by software.
Page 514 GD32G553 User Manual This bit is used to select which timer output controls the comparator output blanking. 0000: No blanking 0001: Select TIMER1_CH2output compare signal as blanking source 0010: Select TIMER7_CH2 output compare signal as blanking source 0011: Select TIMER2_CH2 output compare signal as blanking source...
Page 515 GD32G553 User Manual 1: Reset persist mode. CMP7 output will persist through all resets except for power- on-resets CMP7INTEN CMP7 interrupt enable 0: Disabled 1: Enabled Reserved Must be kept at reset value. CMP7PL Polarity of CMP7 output This bit is used to select the polarity of CMP7 output.
Page 516: Vref
GD32G553 User Manual VREF 20.1. Overview A precision internal reference circuit is inside. The internal voltage reference unit is used to provide voltage reference for ADC / DAC, or used by off-chip circuit connecting to VREFP pin. 20.2. Characteristics ...
Page 517: Vref Calibration
GD32G553 User Manual VREFEN HIPM Mode VREFP pin pulled-down to V External voltage reference mode (default): VREF disabled. off-chip reference voltage injected from VREFP pin. Internal voltage reference mode: VREF enabled. VREFP pin inside connected to VREF output. Hold mode: VREF disabled.
Page 518: Register Definition
GD32G553 User Manual 20.4. Register definition VREF base address: 0x4001 7800 When the DRSTMDy(y=0,1) bit of any DACx(x=0,1,2,3) is set, the VREF registers bit will be retained across all reset events except POR. Control and status register (VREF_CS) 20.4.1. Address offset: 0x00 Reset value: 0x0000 0002 This register can be accessed by half-word (16-bit) or word (32-bit).
Page 519: Calibration Register (Vref_Calib)
GD32G553 User Manual Calibration register (VREF_CALIB) 20.4.2. Address offset: 0x04 Reset value: 0x0000 00XX This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved VREFCAL[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. VREFCAL[5:0]...
Page 520: Watchdog Timer (Wdgt)
GD32G553 User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 521: Figure 21-1. Free Watchdog Block Diagram
GD32G553 User Manual Figure 21-1. Free watchdog block diagram Status: PUD 12-Bit Reset IRC32K Prescaler DownCounter /4/8 256 Reload Control register Reload Status: RUD register The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down. When the counter reaches the value (0x000), there will be a reset.
Page 522: Table 21-1. Min/Max Fwdgt Timeout Period At 32Khz (Irc32K)
GD32G553 User Manual Table 21-1. Min/max FWDGT timeout period at 32KHz (IRC32K) Min timeout (ms) Max timeout (ms) Prescaler PSC[2:0] bits RLD[11:0]= RLD[11:0]= divider 0x000 0xFFF 0.125 0.25 1024 1/16 2048 1/32 4096 1/64 8192 1/128 16384 1/256 110 or 111 32768 The FWDGT timeout can be more accurately by calibrating the IRC32K.
Page 523: Register Definition
GD32G553 User Manual Register definition 21.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 524 GD32G553 User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128 110: 1/256 111: 1/256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit has been reset before changing the prescaler value.
Page 525 GD32G553 User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter window value update When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 526 GD32G553 User Manual These bits are write protected. Write 0x5555 in the FWDGT_CTL register before writing these bits. If several window values are used by the application, it is mandatory to wait until WUD bit has been reset before changing the window value. However, after updating...
Page 527: Window Watchdog Timer (Wwdgt)
GD32G553 User Manual 21.2. Window watchdog timer (WWDGT) Overview 21.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 528: Figure 21-3. Window Watchdog Timing Diagram
GD32G553 User Manual The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 529: Table 21-2. Min-Max Timeout Value At 216 Mhz
GD32G553 User Manual Table 21-2. Min-max timeout value at 216 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 18.96 μs 1.21 ms 37.93 μs 2.43 ms 75.85 μs 4.85 ms 151.70μs 9.71 ms...
Page 530: Register Definition
GD32G553 User Manual Register definition 21.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 531 GD32G553 User Manual operation of 0 has no effect. PSC[1:0] Prescaler. The time base of the watchdog counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4 11: (PCLK1 / 4096) / 8 WIN[6:0] The Window value.
Page 532: Real Time Clock (Rtc)
GD32G553 User Manual Real time clock (RTC) 22.1. Overview The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time.
Page 533: Function Overview
GD32G553 User Manual 22.3. Function overview Block diagram 22.3.1. Figure 22-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre...
Page 534: Clock Source And Prescalers
GD32G553 User Manual Clock source and prescalers 22.3.2. RTC unit has three independent clock sources: LXTAL, IRC32K and HXTAL with divided by 32(configured in RCU_CFG register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions.
Page 535: Configurable Periodic Auto-Wakeup Counter
GD32G553 User Manual masked, the Alarm Flag will assert 3 RTC clock later after ALRMxEN(x=0,1) is set. Configurable periodic auto-wakeup counter 22.3.5. In the RTC block, there is a 16-bit down counter designed to generate periodic wakeup flag. This function is enabled by set the WTEN to 1 and can be running in power saving mode.
Page 536: Daylight Saving Time
GD32G553 User Manual Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps: Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register.
Page 537 GD32G553 User Manual reading calendar time register and date register twice if the two values are equal, the value can be seen as the correct value if the two values are not equal, a third reading should performed the third value can be seen as the correct value RSYNF is asserted once every 2 RTC clock and at this time point, the shadow registers will be updated to current time and date.
Page 538: Resetting The Rtc
GD32G553 User Manual Resetting the RTC 22.3.8. There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT. When system reset is valid, the bits or registers mentioned before are reset to the default value.
Page 539: Rtc Reference Clock Detection
GD32G553 User Manual RTC reference clock detection 22.3.10. RTC reference clock detection is another way to increase the precision of RTC second. To enable this function, you should have an external clock source (50Hz or 60 Hz) which is more precise than LXTAL clock source.
Page 540: Verifying The Rtc Calibration
GD32G553 User Manual So using CMSK can mask clock cycles from 0 to 511 and thus the RTC frequency can be reduced by up to 487.1PPM. To increase the RTC frequency the FREQI bit can be set. If FREQI bit is set, there will be 512 additional cycles to be added during period time which means every 211/210/29(32/16/8 seconds) RTC clock insert one cycle.
Page 541: Re-Calibration On-The-Fly
GD32G553 User Manual the measure is within 0.477PPM (0.5 RTCCLK cycles over 32s).  When the calibration period is 16 seconds(by setting CWND16 bit) In this configuration, CMSK[0] is fixed to 0 by hardware. Using exactly 16s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 0.954PPM...
Page 542 GD32G553 User Manual mode or level detection mode with configurable filtering setting. The purposes of the tamper detect configuration are the following:  The default configuration will erase the RTC backup registers  It can wakeup from DeepSleep and Standby modes, and generate an interrupt.
Page 543: Calibration Clock Output
GD32G553 User Manual writing. Tamper detection is still running when V power is switched off if tamper is enabled. Note: Level detection mode with configurable filtering on tamper input detection When FLT bit is not reset to 0x0, the tamper detection is set to level detection mode and FLT bit determines the consecutive number of samples (2, 4 or 8) needed for valid level.
Page 544: Rtc Power Saving Mode Management
GD32G553 User Manual Table 22-1 RTC pin configuration and function function COEN TP0EN TSEN ALRMOUTTYPE OS[1:0] (output configuration and (calibration (tamper (time stamp (RTC_ALARM selection) pin function output) enabled) enabled) output type Alarm out 01 or 10 or 11 output open drain...
Page 545: Rtc Interrupts
GD32G553 User Manual RTC interrupts 22.3.18. All RTC interrupts are connected to the EXTI controller. Below steps should be followed if you want to use the RTC alarm/tamper/timestamp/auto wakeup interrupt: Configure enable corresponding interrupt line alarm/tamper/timestamp/auto wakeup event of EXTI and set the rising edge for triggering.
Page 546: Register Definition
GD32G553 User Manual 22.4. Register definition RTC base address: 0x4000 2800 Time register (RTC_TIME) 22.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state.
Page 547: Control Register (Rtc_Ctl)
GD32G553 User Manual Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0] Days of the week...
Page 548 GD32G553 User Manual 1: not need RTC Clok ITSEN Internal timestamp event enable 0: Disable Internal timestamp event 1: Enable Internal timestamp event COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output...
Page 549 GD32G553 User Manual ALRM1IE RTC alarm-1 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function...
Page 550: Status Register (Rtc_Stat)
GD32G553 User Manual 0x2:RTC Clock divided by 4 0x3:RTC Clock divided by 2 0x4:0x5: ck_spre (default 1Hz) clock 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. Status register (RTC_STAT) 22.4.4. Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0. Others are not affected Backup domain reset value: 0x0000 0007 This register is writing protected except RTC_STAT[13:8].
Page 551 GD32G553 User Manual Cleared by software writing 0. Time-stamp flag Set by hardware when time-stamp event is detected. Cleared by software writing 0. Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0.
Page 552: Prescaler Register (Rtc_Psc)
GD32G553 User Manual 0: No shift operation is pending 1: Shift function operation is pending WTWF Wakeup timer write enable flag 0: Wakeup timer update is not allowed 1: Wakeup timer update is allowed ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset.
Page 553: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32G553 User Manual This register is writing protected. This register has to be accessed by word (32-bit) Reserved WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits.
Page 554: Alarm 1 Time And Date Register (Rtc_Alrm1Td)
GD32G553 User Manual 1: Mask hour field AM/PM flag 0: AM or 24-hour format 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit 0: Not mask minutes field...
Page 555: Write Protection Key Register (Rtc_Wpk)
GD32G553 User Manual 29:28 DAYT[1:0] Day tens in BCD code 27:24 DAYU[3:0] Day units or week day in BCD code MSKH Alarm hour mask bit 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format...
Page 556: Sub Second Register (Rtc_Ss)
GD32G553 User Manual Sub second register (RTC_SS) 22.4.10. Address offset: 0x28 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register has to be accessed by word (32-bit) Reserved SSC[15:0] Bits Fields Descriptions...
Page 557: Time Of Time Stamp Register (Rtc_Tts)
GD32G553 User Manual down counter: Delay (seconds) = SFS / ( FACTOR_S + 1 ) When jointly using A1S and SFS, the clock will advance: Advance (seconds) = ( 1 - ( SFS / ( FACTOR_S + 1 ) ) ) Note: Writing to this register will cause RSYNF bit to be cleared.
Page 558: Sub Second Of Time Stamp Register (Rtc_Ssts)
GD32G553 User Manual Backup domain reset value: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1. Reset TSF bit will also clear this register. This register has to be accessed by word (32-bit)
Page 559: High Resolution Frequency Compensation Register (Rtc_Hrfc)
GD32G553 User Manual High resolution frequency compensation register (RTC_HRFC) 22.4.15. Address offset: 0x3C Backup domain reset: 0x0000 0000 System Reset: no effect This register is write protected. This register has to be accessed by word (32-bit) Reserved FREQI CWND8 CWND16...
Page 560 GD32G553 User Manual This register has to be accessed by word (32-bit) TP2_DISP Reserved TP2IE TP1IE TP0IE Reserved TP2MASK TP1MASK TP0MASK Reserved Reserved NOERASE NOERASE NOERASE DISPU PRCH[1:0] FLT[1:0] FREQ[2:0] TPTS TP2EG TP2EN TP1EG TP1EN TPIE TP0EG TP0EN Bits Fields...
Page 561 GD32G553 User Manual 0:Tamper 1 event erases the backup registers 1:Tamper 1 event does not erase the backup registers TP0 NOERASE Tamper 0 no erase 0:Tamper 0 event erases the backup registers 1:Tamper 0 event does not erase the backup registers...
Page 562: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32G553 User Manual TP2EG Tamper 2 event trigger edge If tamper detection is in edge mode(FLT =0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event If tamper detection is in level mode(FLT !=0):...
Page 563: Alarm 1 Sub Second Register (Rtc_Alrm1Ss)
GD32G553 User Manual This register is write protected and can only be wrote when ALRM0EN=0 or INITM=1 This register has to be accessed by word (32-bit) Reserved MSKSSC[3:0] Reserved Reserved SSC[14:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value.
Page 564: Configuration Register (Rtc_Cfg)
GD32G553 User Manual This register has to be accessed by word (32-bit) Reserved MSKSSC[3:0] Reserved Reserved SSC[14:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched.
Page 565: Backup Registers (Rtc_Bkpx) (X=0
GD32G553 User Manual Reserved ALRMOUT Reserved OUT2EN TYPE Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. OUT2EN RTC_OUT pin select 0:RTC_OUT is output on PC13 1: RTC_OUT is output on PB2 ALRMOUTTYPE RTC_ALARM Output Type 0: Open-drain output type 1: Push-pull output type Backup registers (RTC_BKPx) (x=0..31)
Page 566: Timer (Timer)
GD32G553 User Manual TIMER (TIMER) Table 23-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7/19 TIMER1/2/3/4 TIMER14 TIMER15/16 TIMER5/6 TYPE Advanced General-L0 General-L3 General-L4 Basic 16-bit 16-bit 16-bit 16-bit 16-bit Prescaler 16-bit(TIMER2/3) 16-bit Counter 16-bit 16-bit 16-bit 32-bit(TIMER1/4) (TIMER5/6)
Page 567 GD32G553 User Manual TIMERx ITI0 ITI1 ITI2 ITI3 ITI4 ITI5 ITI6 ITI7 ITI8 ITI9 ITI10 ITI11 ITI12 ITI13 ITI14 TIMER1_ TIMER2_ TIMER3_ TIMER4 TIMER7_ TIMER14 TIMER15 TIMER16 TIMER19 HRTIME TIMER0 TRGO0 TRGO0 TRGO0 _TRGO0 TRGO0 _TRGO0 _CH0 _CH0 _TRGO0 R_SCOU...
Page 568: Advanced Timer (Timerx, X=0, 7, 19)
GD32G553 User Manual 23.1. Advanced timer (TIMERx, x=0, 7, 19) Overview 23.1.1. The advanced timer module (TIMER0 / 7 / 19) is an eight-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 569: Block Diagram
GD32G553 User Manual Block diagram 23.1.3. Figure 23-1. Advanced timer block diagram provides details of the internal configuration of Table 23-2. Advanced timer channel description the advanced timer, and introduces the input and output of the channels. Figure 23-1. Advanced timer block diagram...
Page 570: Figure 23-2. Normal Mode, Internal Clock Divided By 1
GD32G553 User Manual Internal clock CK_TIMER is selected as timer clock source which is from module RCU. The default clock source is the CK_TIMER for driving the counter prescaler when TSCFGy[4:0] (y = 0...15) = 5’b00000 in SYSCFG_TIMERxCFG(x=0, 7, 19) registers. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK.
Page 571: Clock Prescaler
GD32G553 User Manual source is setting the TSCFG6[4:0] to 0x8. Note that the ETI signal is derived from the ETI pin sampled by a digital filter. When the ETI signal is selected as the clock source, the trigger controller including the edge detection circuitry will generate a clock pulse on each ETI signal rising edge to clock the counter prescaler.
Page 572: Figure 23-4. Timing Diagram Of Up Counting Mode, Psc=0 / 2
GD32G553 User Manual Whenever, if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and an update event will be generated. If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled.
Page 573: Figure 23-5. Timing Diagram Of Up Counting Mode, Change Timerx_Car Ongoing
GD32G553 User Manual Figure 23-5. Timing diagram of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR value ARSE = 1 CNT_REG 114 115 116 117 118 119 120...
Page 574: Figure 23-6. Timing Diagram Of Down Counting Mode, Psc=0 / 2
GD32G553 User Manual Figure 23-6. Timing diagram of down counting mode, PSC=0 / 2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 23-7.
Page 575: Figure 23-8. Timing Diagram Of Center-Aligned Counting Mode
GD32G553 User Manual Center-aligned counting mode In the center-aligned counting mode, the counter counts up from 0 to the counter reload value and then counts down to 0 alternatively. The timer module generates an overflow event when the counter counts to (TIMERx_CAR-1) in the count-up direction and generates an underflow event when the counter counts to 1 in the count-down direction.
Page 576 GD32G553 User Manual Figure 23-8. Timing diagram of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b01 (downcount only CHxIF Hardware set Software clear...
Page 577: Figure 23-9. Repetition Counter Timing Diagram Of Center-Aligned Counting Mode
GD32G553 User Manual value of CREP0/1 is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP0/1 value takes effect. If an update event is generated by software after writing an odd number to CREP0/1, the update events will be generated on the underflow.
Page 578: Figure 23-11. Repetition Counter Timing Diagram Of Down Counting Mode
GD32G553 User Manual Figure 23-11. Repetition counter timing diagram of down counting mode TIMER_CK CNT_CLK CNT_REG 00 63 00 63 00 63 00 63 00 63 Underflow Overflow TIMERx_CREP0 = 0x0 UPIF TIMERx_CREP0 = 0x1 UPIF TIMERx_CREP0 = 0x2 UPIF...
Page 579: Figure 23-12. Input Capture Logic For Channel 0
GD32G553 User Manual Figure 23-12. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture CI1FE0 Clock Register Prescaler Prescaler MCI0FE0 （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channals Figure 23-13.
Page 580: Output Compare Mode
GD32G553 User Manual Based on the input signal and quality of requested signal, configure compatible CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits.
Page 581: Figure 23-15. Output Compare Logic (When Mchxmsel = 2'B11, X=0,1,2,3)
GD32G553 User Manual Figure 23-14. Output compare logic (when MCHxMSEL = 2’b00, x=0, 1, 2, 3) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control polarity selector MCHxCV CHxCOMCTL/ CHxP,CHxEN/ CNT<CHxCV/ MCHx_O MCHxCOMCTL MCHxFP,MCHxEN...
Page 582: Figure 23-16. Output-Compare In Three Modes
GD32G553 User Manual If the output of MOxCPRE is active(high) level, the output of MCHx_O is active(low) level; If the output of MOxCPRE is inactive(low) level, the output of MCHx_O is active(high) level. When MCHxMSEL=2’b11 and CHx_O and MCHx_O are output at the same time, the specific...
Page 583: Figure 23-17. Timing Diagram Of Eapwm
GD32G553 User Manual Figure 23-16. Output-compare in three modes CNT_CLK CNT_REG 03 04 03 04 03 04 Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL / MCHxCOMCTL bit to 4’b0110 (PWM mode 0) or to 4’b0111(PWM mode 1)), the channel can generate PWM waveform according...
Page 584: Adjustment Mode
GD32G553 User Manual Figure 23-17. Timing diagram of EAPWM CARL CHxVAL PWM MODE0 OxCPRE PWM MODE1 OxCPRE Interrupt signal CHxIF CHxOF Figure 23-18. Timing diagram of CAPWM CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CAM=2'b01 down only...
Page 585: Figure 23-19. Adjustment Mode: Data Format And The Register Bit-Field
GD32G553 User Manual 16-fold in resolution. Figure 23-19. Adjustment mode: Data format and the register bit-field bit 19 bit 16 bit 15 bit 0 [19:16] CHxVA L[19:0] the fra ctional [15:0]: the integer part or CARL[19:0] part bit 19 bit 16...
Page 586: Figure 23-20. Pwm Adjustment Mode Schematic Diagram
GD32G553 User Manual Figure 23-20. PWM adjustment mode schematic diagram Counter periods CHxVAL[19:0] 0x10048 Case 1 in 16 periods CHxVAL[19:0] 0x40048 Case 2 in 16 periods 0x50060 CARL[19:0] Case 3 in 16 periods Table 23-3. CHxVAL and CARL bit-field change in edge-aligned...
Page 587: Table 23-4. Chxval And Carl Bit-Field Changes In The Center-Aligned Counting Mode
GD32G553 User Manual Table 23-4. CHxVAL and CARL bit-field changes in the center-aligned counting mode CHxVAL Period [19:16] / CARL Up Down Up Down Up Down Up Down Up Down Up Down Up Down Up Down [19:16] 0000 0001 0010...
Page 588: Figure 23-21. Ch0 And Ch2 With Asymmetric Pwm Mode
GD32G553 User Manual Figure 23-21. CH0 and CH2 with asymmetric PWM mode CARL CH0VAL CH3VAL CH2VAL CH1VAL Asymmetric PWM mode 0 O0CPRE Asymmetric PWM mode 0 O2CPRE Composite PWM mode In the composite PWM mode (CHxCPWMEN = 1’b1, CHxMS[2:0] = 3’b000 and CHxCOMCTL = 4’b0110 or 4’b0111), the PWM signal output in channel x (x=0...3) is composited by CHxVAL...
Page 589: Figure 23-22. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32G553 User Manual Condition Mode PWM pulse width PWM mode 1 (up counting) PWM mode 0(up counting) or PWM mode 1(down counting) CHxCOMVAL_ADD > CARL > PWM mode 0(down CHxVAL counting) or 100% PWM mode 1(up counting) (CHxVAL>CARL) and The output of CHx_O is keeping (CHxCOMVAL_ADD >...
Page 590: Figure 23-23. Channel X Output Pwm With (Chxval = Chxcomval_Add)
GD32G553 User Manual  CHxVAL = CHxCOMVAL_ADD, and the value of CHxVAL and CHxCOMVAL_ADD between 0 and CARL. Figure 23-23. Channel x output PWM with (CHxVAL = CHxCOMVAL_ADD) CARL CARL CHxVAL = CHxCOMVAL_ADD CHxVAL = CHxCOMVAL_ADD Constant “0” Constant “0”...
Page 591: Figure 23-26. Channel X Output Pwm Duty Cycle Changing With Chxcomval_Add
GD32G553 User Manual CHxCOMVAL_ADD CHxVAL CARL CARL CHxCOMVAL_ADD CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF The composite PWM mode is intended to support the generation of PWM signals where the period is not modified while the signal is being generated, but the duty cycle will be varied.
Page 592: Figure 23-28. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel≠2'B00)
GD32G553 User Manual CARL CH1COMVAL_ADD CH3VAL CH0COMVAL_ADD CH2VAL CH1VAL CH0VAL CH3COMVAL_ADD CH2COMVAL_ADD PWM Mode 1 O0CPRE O1CPRE O2CPRE O3CPRE Output match pulse select Basing on that CHx_O (x=0...3) outputs are configured by CHxCOMCTL[3:0](x=0...3) bits when the match events occur, the output signal is configured by CHxOMPSEL[1:0](x=0...3) bit to be normal or a pulse.
Page 593: Figure 23-29. Chx_O Output With A Pulse In Center-Aligned Mode (Chxompsel≠2'B00)
GD32G553 User Manual CHxOMPS EL=2 b01 CHxOMPS EL=2 b10 CHxOMPS EL=2 b11 Figure 23-29. CHx_O output with a pulse in center-aligned mode (CHxOMPSEL≠2’b00) CHxOMPS EL=2 b01 CHxOMPS EL=2 b10 CHxOMPS EL=2 b11 Channel output prepare signal Figure 23-14. Output compare logic (when MCHxMSEL = 2’b00, x=0, 1, 2, As is shown in Figure 23-15.
Page 594 GD32G553 User Manual by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 / PWM mode 1 output is another output type of OxCPRE which is setup by configuring the CHxCOMCTL field to 0x06 / 0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 595: Table 23-6. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32G553 User Manual Separated dead channels has separated deadtime value and break function, please refer to time insertion and Break function), ISOx and ISOxN bits in the TIMERx_CTL1 register. The output polarity is determined by CHxP and MCHxP bits in the TIMERx_CHCTL2 register.
Page 596: Figure 23-30. Complementary Output With Dead Time Insertion
GD32G553 User Manual with GPIO pull up / down setting which will be Hi-Z if no pull. (6) “off-state”: CHx_O / MCHx_O output with inactive state (e.g., CHx_O = 0⊕CHxP = CHxP). (7) See Break mode section for more details.
Page 597: Figure 23-31. Complementary Output With Different Dead Time(Dtdifen=1)
GD32G553 User Manual Separated dead time insertion and Break function. By configuring the DTIENCHx (x=0...3) bit in the TIMERx_CTL2 register to realize the independent control of dead-time insertion function for each pair of channels. When the DTIENCHx (x=0...3) bit is “0”, the corresponding channels CHx_O and MCHx_O will not be inserted into the dead-time.
Page 598: Figure 23-32. Break0 Function Logic Diagram
GD32G553 User Manual bits in the TIMERx_CCHP0 register, ISOx and ISOxN bits in the TIMERx_CTL1 register. The break event is the result of logic ORed of all sources. The break functions can handle three types of event sources:  External sources: coming from BRKINx (x=0...2) inputs;...
Page 599: Figure 23-34. Output Behavior Of The Channel In Response To Break0 (The Break Input High Active And Ios=1)
GD32G553 User Manual ISOx and ISOxN bits in the TIMERx_CTL1 register. If IOS = 0, the timer releases the enable output, otherwise, the enable output remains high. When IOS=1, the output behavior of the Figure 23-34. Output behavior of the channel in response to BREAK0...
Page 600: Figure 23-35. Output Behavior Of The Channel Outputs With The Break0 And Break1
GD32G553 User Manual Figure 23-35. Output behavior of the channel outputs with the BREAK0 and BREAK1 CHxP=MCHxP=0, BRK0P=BRK1P=0, ISOx=0,ISOxN=1 IOS=0 BREAK0 OxCPRE Control by GPIO CHx_O Control by GPIO MCHx_O Deadtime IOS=1 BREAK0 BREAK1 CHx_O MCHx_O Deadtime Deadtime When CHx_O and MCHx_O channels has separated break function, please refer to Separated dead time insertion and Break function.
Page 601: Figure 23-36. Brkinx (X=0
GD32G553 User Manual TIMERx_CCHP0 register. When the break input sources are inactive, the BRK0REL / BRK1REL bit will cleared by hardware and the BRKINx (x=0...2) pin will restore the locked break function. In the following two cases, the BRKINx (x=0...2) pin cannot be released: ...
Page 602: Table 23-9. Counting Direction In Different Quadrature Decoder Signals
GD32G553 User Manual TIMERx_FCCHPy(y=0...3) register. By configuring the FCCHPyEN (y=0...3) bits in the TIMERx_FCCHPy (y=0...3) registers can select whether each pair of channels uses the separated dead time insertion and break function. When the FCCHPyEN=0, the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP0 register is active;...
Page 603: Figure 23-37. Example Of Counter Operation In Decoder Interface Mode
GD32G553 User Manual Figure 23-37. Example of counter operation in decoder interface mode CI0FE0 CI1FE1 Counter down Figure 23-38. Example of decoder interface mode with CI0FE0 polarity inverted When the counter direction changes in the quadrature decoder modes, the DIR bit in TIMERx_CTL0 register within a change, at the same time the DIRTRANIF bit in TIMERx_INTF is set to 1.
Page 604: Figure 23-39. Quadrature Decoder Signal Disconnection Detection Block Diagram
GD32G553 User Manual diagram. The signal detection module includes two 32-bit watchdog counters and a period register. The CI0 and CI1 signals are used to reset the two watchdog counters respectively. When DECDISDEN=1, two watchdog counters start counting up at the same time. If the...
Page 605: Figure 23-40. Example Of Counter Operation In Decoder Mode 0 / 1 With Ch1P=0
GD32G553 User Manual Table 23-10. the counter operation in decoder mode 1 CH1P level counter operation CI0FE0 is high the counter will count up on the rising edge of the CI1FE1 input signal CI0FE0 is low the counter will count down on the rising edge of the CI1FE1 input signal...
Page 606: Figure 23-41. Example Of Counter Operation In Decoder Mode 2 / 3 (Ch0P / Ch1P=0)
GD32G553 User Manual Figure 23-41. Example of counter operation in decoder mode 2 / 3 (CH0P / CH1P=0) CI0FE0 CI1FE1 Decoder mode 3 Counter Decoder mode 2 Counter Table 23-11. the counter operation in decoder mode 2 / 3 CI0FE0...
Page 607: Figure 23-42. Three Types Of Index Signals
GD32G553 User Manual by setting the MMC0[3:0] bit-field to 4’b1000 in the TIMERx_CTL1 register, and just used in quadrature decoder mode 0~4 and decoder mode 0~3. Index input function Index input for quadrature decoder There are three output signals are commonly used in decoder: A pulse, B pulse and 1 is the location of reference index of the pulse signal.
Page 608: Figure 23-43. Counter With The Index Signal The Same As A (Indp[1:0]=2'B11)
GD32G553 User Manual  The counter is reset (DIR bit is 0) when counting up;  The counter is set to the value of theTIMERx CAR register (DIR bit is 1) when counting down. This ensures that the index pulse is always generated at the same mechanical angle regardless of the up counting mode or down counting mode.
Page 609: Figure 23-44. The Relationship Between The Index Signal And Counter Reset Events
GD32G553 User Manual Figure 23-44. The relationship between the index signal and counter reset events Counter DIR bit Index Input event INDRSTDIR[1:0]=2b 00 INDRSTDIR[1:0]=2b 01 INDRSTDIR[1:0]=2b 10 First index signal reset the counter The first index signal reset counter function can enable by configuring the FINDRST bit to 1 in the TIMERx_DECCTL register.
Page 610: Figure 23-46. The Index Error Detection In Up Counting Mode
GD32G553 User Manual corresponding interrupt is generated if the INDIE bit in TIMERx_DMAINTEN register is set to1. Index error detection IIf there is no index pulse is detected, an index error is generated, when the counter counts up from the value of TIMERx CAR register to 0 or counts down from 0 to the value of TIMERx CAR register.
Page 611: Figure 23-47. Hall Sensor Is Used For Bldc Motor
GD32G553 User Manual Hall sensor function Hall sensor is generally used to control BLDC motor; the advanced timer supports this function. Figure 23-47. Hall sensor is used for BLDC motor shows how to connect the timer and the motor. And two timers are needed. TIMER_in(Advanced / General L0 TIMER）is used to accept three rotor position signals of motor from hall sensors.
Page 612: Figure 23-48. Hall Sensor Timing Between Two Timers
GD32G553 User Manual Figure 23-48. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O MCH0_O CH1_O MCH1_O CH2_O MCH2_O Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode and so on, which is selected by the TSCFGy[4:0] (y=3..8) in...
Page 613: Figure 23-49. Restart Mode
GD32G553 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 01001: ITI4 output external used 01010: ITI5 trigger input ETI) is configuring ETFC and 01011: ITI6 selected as the trigger prescaler can be used 01100: ITI7 source, configure the by configuring ETPSC.
Page 614: Figure 23-50. Pause Mode
GD32G553 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 23-50. Pause mode Event mode ETPSC = 1, ETI is The counter will start to TSCFG5[4:0] ETP = 0, the polarity divided by 2. =5’b01000, count when a rising...
Page 615: Figure 23-52. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
GD32G553 User Manual Once the timer is set to the single pulse mode, it is not necessary to configure the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter. Setting the CEN bit to 1 or a trigger signal edge can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 616: Figure 23-53. Delayable Single Pulse Mode With Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32G553 User Manual update event; When counting down, the OxCPRE / MOxCPRE is inactive, when a trigger event occurs, the OxCPRE / MOxCPRE is active. The OxCPRE / MOxCPRE is inactive again at the next update event. In delayable mode 1. The behavior of OxCPRE / MOxCPRE is performed as in PWM mode 1.
Page 617: Figure 23-54. Programmable Pulse Output Circuity
GD32G553 User Manual Figure 23-54. Programmable pulse output circuity Set / Reset Reset CH2_O CH2COMCTL Pulse generator CH3COMCTL CH3_O OPPSC[2:0] OPWID[7:0] Set / Reset Reset This mode can be used in three counter counting modes (up counting, down counting, and center-aligned counting) and all slave modes.
Page 618: Figure 23-56. Ch2_O And Ch3_O Output The Pulse At The Same Time
GD32G553 User Manual Figure 23-56. CH2_O and CH3_O output the pulse at the same time CARL CH3VAL CH2VAL compare match event CH2_O CH3_O Timers interconnection The timers can be internally connected for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode.
Page 619: Figure 23-57. Trigger Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32G553 User Manual 2. Configure TIMER0 in event mode and select the TIMER2 as TIMER0 input trigger source (TRCFG5[4:0] = 5’b00011 in the_SYSCFG_TIMER0CFG0 register). 3. Start TIMER2 by writing 1 to the CEN bit (TIMER2_CTL0 register). Figure 23-57. Trigger mode of TIMER0 controlled by enable signal of TIMER2...
Page 620: Figure 23-59. Pause Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32G553 User Manual divided internal clock only when TIMER2 is enabled. Both clock frequency of the counters is divided by 3 from TIMER_CK (f / 3). Steps are shown as follows: PSC_CLK TIMER_CK 1. Configure TIMER2 in master mode and output enable signal as trigger output (MMC0=4’b0001 in the TIMER2_CTL1 register).
Page 621: Figure 23-60. Pause Mode Of Timer0 Controlled By O0Cpre Signal Of Timer2
GD32G553 User Manual Figure 23-60. Pause mode of TIMER0 controlled by O0CPRE signal of TIMER2 Using an external trigger to start two timers synchronously.  The start of TIMER0 is triggered by the enable signal of TIMER2, and TIMER2 is triggered by its CI0 input rising edge.
Page 622: Figure 23-61. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32G553 User Manual Figure 23-61. Trigger TIMER0 and TIMER2 by the CI0 signal of TIMER2 TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Counter synchronization and counter initial direction and value refresh In some timer daisy chain configurations, multiple timers are triggered and synchronized to start counting at the same time.
Page 623: Figure 23-62. Configurable Phase Method Diagram
GD32G553 User Manual Figure 23-62. Configurable phase method diagram TIMER0 Configured in restart +event mode Counter initial value = 16'd0 Trigger TIMER7 Configured in restart +event mode TIMER1 Counter initial value = 16'd20 TIMER19 Configured in restart +event mode Counter refresh value = 16'd40 Figure 23-63.
Page 624: Figure 23-64. Direction Of The Counter After The Reset In Center-Aligned Counting Mode
GD32G553 User Manual Figure 23-64. Direction of the counter after the reset in center-aligned counting mode trigger in trigger in CINITDIR=0 CARL=100 CINITV AL=20 counter=0 CINITDIR=1 CARL=100 CINITV AL=20 counter=0 The counter initial direction and value also can refresh by soft synchronization event. When SWSYNCG bit in TIMERx_CINITCTL register is set, a soft synchronization event generated, and TIMERx can refresh the counter initial direction and value.
Page 625 GD32G553 User Manual When the counter works in center-aligned counting mode, this function can be used to indicates the counter direction of the counter. When the counter works in decoder modes, this function can be used to indicates the rotation direction for the external signal.
Page 626: Registers Definition (Timerx, X=0, 7, 19)
GD32G553 User Manual Registers definition (TIMERx, x=0, 7, 19) 23.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 TIMER19 base address: 0x4001 5000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 627 GD32G553 User Manual 1: The shadow register for TIMERx_CAR register is enabled CAM[1:0] Counter align mode selection 00: No center-aligned mode (edge-aligned mode). The direction of the counter is specified by the DIR bit. 01: Center-aligned and counting down assert mode. The counter counts in center- aligned mode and channel is configured in output mode (CHxMS = 3’b000 in...
Page 628 GD32G553 User Manual 1: Update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UG bit is set or the slave mode controller generates a hardware reset event. Counter enable 0: Counter disable...
Page 629 GD32G553 User Manual 010: Update. In this mode, the master mode controller selects the update event as TRGO1. 011: Capture / compare pulse. In this mode, the master mode controller generates a TRGO1 pulse when a capture or a compare match occurs in channel 0.
Page 630 GD32G553 User Manual 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, TIMERx_CH1 and TIMERx_CH2 pins is selected as channel 0 trigger input. MMC0[2:0] Master mode control 0 These bits control the selection of TRGO0 signal, which is sent by master timer to slave timer for synchronization function.
Page 631 GD32G553 User Manual 001: The shadow registers update when CMTG bit is set or a rising edge of TRGI occurs. 100: The shadow registers update when the counter generates an overflow event. 101: The shadow registers update when the counter generates an underflow event.
Page 632 GD32G553 User Manual 1: Decoder mode is updated by the index event after the modification. DECMODEN Decoder mode modified on-the-fly enable 0: Decoder mode modified on-the-fly disable. 1: Decoder mode modified on-the-fly enable. When this bit is set to 1, the decoder mode can be modified from one mode to another mode.
Page 633 GD32G553 User Manual 0110: f / 4, N=6. SAMP 0111: f / 4, N=8. SAMP 1000: f / 8, N=6. SAMP 1001: f / 8, N=8. SAMP 1010: f / 16, N=5. SAMP 1011: f / 16, N=6. SAMP 1100: f / 16, N=8.
Page 634 GD32G553 User Manual Note: This bit just used in composite PWM mode. CH2COMADDIE Channel 2 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode. CH1COMADDIE Channel 1 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode.
Page 635 GD32G553 User Manual 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MCH2MSEL[1:0] = 2’b00). MCH1IE Multi mode channel 1 capture / compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MMCH1SEL[1:0] = 2’b00).
Page 636 GD32G553 User Manual 1: Enabled CH3DEN Channel 3 capture / compare DMA request enable 0: Disabled 1: Enabled CH2DEN Channel 2 capture / compare DMA request enable 0: Disabled 1: Enabled CH1DEN Channel 1 capture / compare DMA request enable...
Page 637 GD32G553 User Manual UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DIRTRANI CH3COM CH2COM CH1COM CH0COM MCH0IF INDERRIF DECDISIF DECJIF...
Page 638 GD32G553 User Manual cleared by software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred MCH3IF Multi mode channel 3 capture / compare interrupt flag Refer to MCH0IF description MCH2IF Multi mode channel 2 capture / compare interrupt flag...
Page 639 GD32G553 User Manual This flag is set by hardware and cleared by software. 0: No Index interrupt occurred 1: Index interrupt occurred Reserved Must be kept at reset value. SYSBIF System source break interrupt flag This flag is set by hardware when the system sources are active, and cleared by software if the system sources are inactive.
Page 640 GD32G553 User Manual 0: No trigger event occurred 1: Trigger interrupt occurred CMTIF Channel commutation interrupt flag This flag is set by hardware when the commutation event of channel occurs, and cleared by software. 0: No channel commutation interrupt occurred...
Page 641 GD32G553 User Manual Refer to CH0COMADDG description. CH2COMADDG Channel 2 additional compare event generation. Refer to CH0COMADDG description. CH1COMADDG Channel 1 additional compare event generation. Refer to CH0COMADDG description. CH0COMADDG Channel 0 additional compare event generation. This bit is set by software to generate a compare event in channel 0 additional, it is automatically cleared by hardware.
Page 642 GD32G553 User Manual automatically. When this bit is set, the POEN bit will be cleared and BRK0IF flag will be set. 0: No generate a BREAK0 event 1: Generate a BREAK0 event TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_INTF register will be set, related interrupt or DMA transfer can occur if enabled.
Page 643 GD32G553 User Manual Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1ADDU CH0ADDU CH1COM CH0COM CH1COM CH0COM CH1MS CH0MS ADDSEN ADDSEN CTL[3] CTL[3] Reserved Reserved Reserved Reserved...
Page 644 GD32G553 User Manual Reserved Must be kept at reset value. CH1COMCTL[3] Channel 1 compare output control Refer to CH0COMCTL[2:0] description 23:17 Reserved Must be kept at reset value. CH0COMCTL[3] Channel 0 compare output control Refer to CH0COMCTL[2:0] description CH1COMCEN Channel 1 output compare clear enable...
Page 645 GD32G553 User Manual drives CH0_O and MCH0_O. The active level of O0CPRE is high, while the active level of CH0_O and MCH0_O depends on CH0P and MCH0P bits. 0000: Timing mode. The O0CPRE signal keeps stable, independent of the comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT.
Page 646 GD32G553 User Manual When the outputs of CH0 and MCH0 are complementary, this bit-field is preloaded. If CCSE =1, this bit-field will only be updated when a channel commutation event is generated. This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP0 register is 11 and CH0MS bit-field is 000 (compare mode).
Page 647 GD32G553 User Manual Same as output compare mode. CH0MS[2] Channel 0 I / O mode selection Same as output compare mode. 29:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description.
Page 648 GD32G553 User Manual Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3ADDU CH2ADDU CH3COM CH2COM CH3COM CH2COM CH3MS CH2MS ADDSEN ADDSEN CTL[3] CTL[3] Reserved Reserved Reserved Reserved Reserved...
Page 649 GD32G553 User Manual Reserved Must be kept at reset value. CH3COMCTL[3] Channel 3 compare output control Refer to CH2COMCTL[2:0] description 23:17 Reserved Must be kept at reset value. CH2COMCTL[3] Channel 2 compare output control Refer to CH2COMCTL[2:0] description CH3COMCEN Channel 3 output compare clear enable...
Page 650 GD32G553 User Manual level of CH2_O and MCH2_O depends on CH2P and MCH2P bits. 0000: Timing mode. The O2CPRE signal keeps stable, independent of the comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT. 0001: Set the channel output on match. O2CPRE signal is forced high when the counter matches the output compare register TIMERx_CH2CV.
Page 651 GD32G553 User Manual the PWM signal output in channel 2 is composited by TIMERx_CH2CV and TIMERx_CH2COMV_ADD. Please refer to Composite PWM mode for more details. If configured in PWM mode, the O2CPRE level changes only when the output compare mode switches from “Timing” mode to “PWM” mode or the result of the comparison changes.
Page 652 GD32G553 User Manual 100: Channel 2 is configured as input, IS2 is connected to MCI2FE2. 101~111: Reserved. Input capture mode: Bits Fields Descriptions CH3MS[2] Channel 3 I / O mode selection Same as output compare mode. CH2MS[2] Channel 2 I / O mode selection Same as output compare mode.
Page 653 GD32G553 User Manual 01: Capture is done every 2 channel input edges. 10: Capture is done every 4 channel input edges. 11: Capture is done every 8 channel input edges. CH2MS[1:0] Channel 2 mode selection Same as output compare mode.
Page 654 GD32G553 User Manual Refer to MCH0P description. MCH1EN Multi mode channel 1 output enable Refer to MCH0EN description. CH1P Channel 1 capture / compare polarity Refer to CH0P description. CH1EN Channel 1 capture / compare enable Refer to CH0EN description.
Page 655 GD32G553 User Manual in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel 0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 656 GD32G553 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 657 GD32G553 User Manual Reserved CREP0[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP0[7:0] Counter repetition value 0 This bit-field specifies the update event generation rate. Each time the repetition counter counts down to zero, an update event will be generated. The update rate of the shadow registers is also affected by this bit-field when these shadow registers are enabled.
Page 658 GD32G553 User Manual When the PWMADMEN =1, CH0VAL[15:0] bit-field specifies integer part of the compare value. Channel 1 capture compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1VAL[19:16]...
Page 659 GD32G553 User Manual CH2VAL[19:16] Reserved CH2VAL[15:0] Bits Fields Descriptions 31:28 CH2VAL[19:16] Capture / compare value of channel 2 (bit 16 to 19) When channel 2 is configured in input mode, CH2VAL[19:16] bit-field is 0000. When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 660 GD32G553 User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. When the PWMADMEN = 0, the CH3VAL[19:16] bit-field is 0000. When the PWMADMEN =1, CH3VAL[19:16] bit-field specifies the fractional part.
Page 661 GD32G553 User Manual Note: Every write operation to this bit needs a delay of 1 APB clock to active. BRK1REL BREAK1 input released Refer to BRK0REL description. BRK0REL BREAK0 input released This bit is cleared by hardware when the BREAK0 input is invalid.
Page 662 GD32G553 User Manual 1011: f / 16, N=6 SAMP 1100: f / 16, N=8 SAMP 1101: f / 32, N=5 SAMP 1110: f / 32, N=6 SAMP 1111: f / 32, N=8 SAMP This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 663 GD32G553 User Manual This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK0P BREAK0 input signal polarity This bit specifies the polarity of the BREAK0 input signal. 0: BREAK0 input active low 1: BREAK0 input active high This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 664 GD32G553 User Manual bits in TIMERx_CHCTL2 register (if related channel is configured in output mode), the ROS / IOS bits in TIMERx_CCHP0 register and the ROS / IOS bits in TIMERx_FCCHPx (x = 0...3) register are writing protected. 11: PROT mode 2. In addition to the registers in PROT mode 1, the CHxCOMCTL...
Page 665 GD32G553 User Manual 29:25 Reserved Must be kept at reset value. MCH1COMCTL Multi mode channel 1 compare output control. Refer to MCH0COMCTL[2:0] description. 23:17 Reserved Must be kept at reset value. MCH0COMCTL Multi mode channel 0 compare output control. Refer to MCH0COMCTL[2:0] description.
Page 666 GD32G553 User Manual MCH0_O depends on CH0P and MCH0P bits. 0000: Timing mode. The MO0CPRE signal keeps stable, independent of the comparison between register TIMERx_MCH0CV counter TIMERx_CNT. 0001: Set the channel output on match. MO0CPRE signal is forced high when the counter matches the output compare register TIMERx_MCH0CV.
Page 667 GD32G553 User Manual 0: Multi mode channel 0 output compare shadow disabled 1: Multi mode channel 0 output compare shadow enabled The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set).
Page 668 GD32G553 User Manual MCH1MS[1:0] Multi mode channel 1 I / O mode selection. Same as output compare mode. MCH0CAPFLT[3:0] Multi mode channel 0 input capture filter control. An event counter is used in the digital filter, in which a transition on the output occurs after N input events.
Page 669 GD32G553 User Manual MCH3CO MCH3CO MCH3CO MCH2CO MCH2CO MCH2CO MCH3COMCTL[2:0] MCH2COMCTL[2:0] MCEN MSEN MFEN MCEN MSEN MFEN MCH3MS[1:0] MCH2MS[1:0] MCH3CAPFLT[3:0] MCH3CAPPSC[1:0] MCH2CAPFLT[3:0] MCH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions MCH3MS[2] Multi mode channel 1 I / O mode selection Refer to MCH3MS[1:0]description.
Page 670 GD32G553 User Manual MCH2COMCEN Multi mode channel 2 output compare clear enable. When this bit is set, the MO2CPRE signal is cleared when high level is detected on ETIFP input. 0: Multi mode channel 2 output compare clear disabled 1: Multi mode channel 2 output compare clear enabled...
Page 671 GD32G553 User Manual MO2CPRE is inactive. The MO2CPRE is active again at the next update event. 1010~1111: Reserved. If configured in PWM mode, the MO2CPRE level changes only when the output compare mode switches from “Timing” mode to “PWM” mode or the result of the comparison changes.
Page 672 GD32G553 User Manual Input capture mode: Bits Fields Descriptions MCH3MS[2] Multi mode channel 1 I / O mode selection Refer to MCH3MS[1:0]description. MCH2MS[2] Multi mode channel 0 I / O mode selection Refer to MCH2MS[1:0] description. 29:16 Reserved Must be kept at reset value.
Page 673 GD32G553 User Manual MCH2MS[1:0] Multi mode channel 2 I / O mode selection Same as output compare mode. Multi mode channel control register 2 (TIMERx_MCHCTL2) Address offset: 0x50 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit).
Page 674 GD32G553 User Manual This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP0 register is 11 or 10. Multi mode channel 0 capture compare value register (TIMERx_MCH0CV) Address offset: 0x54 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 675 GD32G553 User Manual When multi mode channel 1 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Multi mode channel 2 capture...
Page 676 GD32G553 User Manual counter value at the last capture event. And this bit-field is read-only. When multi mode channel 3 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 677 GD32G553 User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Note: This register just used in composite PWM mode(when CH0CPWMEN=1). Channel 2 additional compare value register (TIMERx_CH2COMV_ADD) Address offset: 0x6C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 678 GD32G553 User Manual shadow register updates by every update event. Note: This register just used in composite PWM mode(when CH0CPWMEN=1). Control register 2 (TIMERx_CTL2) Address offset: 0x74 Reset value: 0x0FF0 00FF This register has to be accessed by word (32-bit).
Page 679 GD32G553 User Manual 11: Complementary mode, only the CH2 is valid for input, and the outputs of MCH2 and CH2 are complementary 23:22 MCH1MSEL[1:0] Multi mode channel 1 mode select 00: Independent mode, MCH1 is independent of CH1 01: Reserved...
Page 680 GD32G553 User Manual when the match events occurs, and the pulse width is one CK_TIMER clock cycle. 10: Only when the counter is counting down, the O2CPRE signal is output a pulse when the match events occurs, and the pulse width is one CK_TIMER clock cycle.
Page 681 GD32G553 User Manual 1: Enabled DTIENCH3 Dead time inserted enable for channel 3 Enables the deadtime insertion in the outputs of MCH3_O and CH3_O. 0: Disabled 1: Enabled DTIENCH2 Dead time inserted enable for channel 2 Enables the deadtime insertion in the outputs of MCH2_O and CH2_O.
Page 682 GD32G553 User Manual This bit-field controls the value of the dead-time on the falling edge of OxCPRE, which is inserted before the output transitions. The relationship between DTCFG value and the duration of dead-time is as follow: DTCFG [7:5] =3’b0xx: DTvalue = DTCFG [7:0]x t DTCFG [7:5] =3’b10x: DTvalue = (64+DTCFG [5:0])xt...
Page 683 GD32G553 User Manual Free complementary channel protection register 1 (TIMERx_FCCHP1) Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). This register is used to configure the outputs of CH1_O / MCH1_O. FCCHP1 Reserved...
Page 684 GD32G553 User Manual is 10 or 11. Idle mode off-state configure When POEN bit is reset, this bit specifies the output state for the channels which has been configured in output mode. 0: When POEN bit is reset, the channel output signals (CH1_O / MCH1_O) are disabled.
Page 685 GD32G553 User Manual is 00. 30:24 Reserved Must be kept at reset value. 23:16 DTFCFG[7:0] Dead time falling edge configure This bit-field controls the value of the dead-time on the falling edge of OxCPRE, which is inserted before the output transitions. The relationship between DTCFG value and the duration of dead-time is as follow: DTCFG [7:5] =3’b0xx: DTvalue = DTCFG [7:0]x t...
Page 686 GD32G553 User Manual This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP0 register is 00. Free complementary channel protection register 3 (TIMERx_FCCHP3) Address offset: 0x88 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 687 GD32G553 User Manual 1: When POEN bit is set, the channel output signals (CH3_O / MCH3_O) are enabled, with relationship to CH3EN / MCH3EN bits in TIMERx_CHCTL2 register. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP0 register is 10 or 11.
Page 688 GD32G553 User Manual BRK0CMP3P BREAK0 CMP3 input polarity This bit is used to configure the CMP3 input polarity, and the specific polarity is determined by this bit and the BRK0P bit. 0: CMP3 input signal will not be inverted (BRK0P =0, the input signal is active low;...
Page 689 GD32G553 User Manual BRK0P =1, the input signal is active high) 1: BRKIN2 input signal will be inverted (BRK0P=0, the input signal is active high; BRK0P =1, the input signal is active low) This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 690 GD32G553 User Manual This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK0CMP2EN BREAK0 CMP2 enable 0: CMP2 input disabled 1: CMP2 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 691 GD32G553 User Manual is 00. BRK0IN0EN BREAK0 BRKIN0 alternate function input enable 0: BRKIN0 alternate function input disabled 1: BRKIN0 alternate function input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. Alternate function control register 1 (TIMERx_AFCTL1)
Page 692 GD32G553 User Manual BRK1CMP1P BREAK1 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specific polarity is determined by this bit and the BRK1P bit. 0: CMP1 input signal will not be inverted (BRK1P =0, the input signal is active low;...
Page 693 GD32G553 User Manual BRK1P =1, the input signal is active low) This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK1IN1P BREAK1 BRKIN1 alternate function input polarity This bit is used to configure the BRKIN1 input polarity, and the specific polarity is determined by this bit and the BRK1P bit.
Page 694 GD32G553 User Manual is 00. BRK1CMP2EN BREAK1 CMP2 enable 0: CMP2 input disabled 1: CMP2 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK1CMP1EN BREAK1 CMP1 enable 0: CMP1 input disabled 1: CMP1 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 695 GD32G553 User Manual 0: BRKIN0 alternate function input disabled 1: BRKIN0 alternate function input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. Watchdog counter period register(TIMERx_WDGPER) Address offset: 0x94 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit).
Page 696 GD32G553 User Manual the shadow registers is also affected by this bit-field when these shadow registers are enabled. Note: This bit-field just used with CREPSEL =1(in TIMERx_CFG register). Complementary channel protection register 1 (TIMERx_CCHP1) Address offset: 0x09C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 697 GD32G553 User Manual DTCFG [7:5] =3’b0xx: DTvalue = DTCFG [7:0]x t DTCFG [7:5] =3’b10x: DTvalue = (64+DTCFG [5:0])xt DTCFG [7:5] =3’b110: DTvalue = (32+DTCFG [4:0])xt DTCFG [7:5] =3’b111: DTvalue = (32+DTCFG [4:0])xt *16. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP0 register is 00.
Page 698 GD32G553 User Manual Note: In decoder modes 0~3, INDP[1] bit is no use. FINDRST First index signal reset the counter 0: All the index signals are can reset the counter 1: Only the first index signal is active and can reset the counter Reserved Must be kept at reset value.
Page 699 GD32G553 User Manual This bit indicates the initial direction of the counter after a synchronization event occurs and the counter initial value is loaded from the TIMERx_CINITV register. Note: This bit is only used when the CAM[1:0] ≠ 00. CINITVEN Counter initial value register enable 0: Counter initial value register disable.
Page 700 GD32G553 User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 DMATC[5:0] DMA transfer count This field defines the times of accessing (R / W) the TIMERx_DMATB register by DMA. 6’b000000: transfer 1 time 6’b000001: transfer 2 times …...
Page 701 GD32G553 User Manual Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CCUSEL CREPSEL CHVSEL OUTSEL Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CCUSEL Commutation control shadow register update select This bit is valid only when the CCUC[2:0] bit-field are set to 100, 101 and 110.
Page 702: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32G553 User Manual 23.2. General level0 timer (TIMERx, x=1, 2, 3, 4) Overview 23.2.1. The general level0 timer module (TIMER1 / 2 / 3 / 4) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 703: Function Overview
GD32G553 User Manual Figure 23-65. General Level 0 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TIMERx_TRGO0 Trigger selector CH0_I Input Logic CH1_I Synchronizer&Filter Edge selector Prescaler CH2_I &Edge Detector CH3_I TIMERx_CHxCV Counter External Trigger Input logic On-chip ETI PSC_CLK sources Polarity selection TIMER_CK...
Page 704: Clock Prescaler
GD32G553 User Manual Figure 23-66. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK 20 21 01 02 CNT_REG TSCFG6[4:0] are setting to a nonzero value (external clock mode 0). External input pin is selected as timer clock source.
Page 705: Figure 23-67. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32G553 User Manual be changed ongoing, but it is adopted at the next update event. Figure 23-67. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB Reload Pulse PSC value Prescaler BUF Prescaler CNT...
Page 706 GD32G553 User Manual Figure 23-68. Timing chart of up counting mode, PSC=0 / 2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 23-69.
Page 707: Figure 23-70. Timing Chart Of Down Counting Mode, Psc=0 / 2
GD32G553 User Manual Down counting mode In this mode, the counter counts down continuously from the counter reload value, which is defined in the TIMERx_CAR register, in a count-down direction. Once the counter reaches 0, the counter restarts to count again from the counter reload value. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode.
Page 708: Figure 23-71. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32G553 User Manual Figure 23-71. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR value ARSE = 1 CNT_REG 119 118...
Page 709: Figure 23-72. Timing Chart Of Center-Aligned Counting Mode
GD32G553 User Manual Figure 23-72. Timing chart of center-aligned counting mode updated. shows the example of the counter behavior when TIMERx_CAR=0x99, TIMERx_PSC=0x0. Figure 23-72. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11...
Page 710: Figure 23-73. Input Capture Logic
GD32G553 User Manual enabled when CHxIE=1. Figure 23-73. Input capture logic Edge Detector Synchronizer Edge selector &inverter Filter Based on CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture Clock Counter CI1FE0 Register Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other...
Page 711: Figure 23-74. Output Compare Logic (X=0,1,2,3)
GD32G553 User Manual The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connects to CI0 input. Select CI0 as channel 0 capture signals by setting CH0MS to 3’b001 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 712: Figure 23-75. Output-Compare Under Three Modes
GD32G553 User Manual Step3: Interrupt / DMA-request enables configuration by CHxIE / CHxDEN. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed ongoing to meet the expected waveform. Step5: Start the counter by configuring CEN to 1.
Page 713: Adjustment Mode
GD32G553 User Manual be always inactive in PWM mode 1 (CHxCOMCTL=4’b0111). Figure 23-76. Timing chart of EAPWM Figure 23-77. Timing chart of CAPWM CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CAM=2'b01 down only CHxIF CHxOF...
Page 714: Figure 23-78. Adjustment Mode: Data Format And The Register Bit-Field
GD32G553 User Manual [27:0] bit-field (TIMER1 / 4) for CHxVAL bit-field and CARL bit-field are used for the integer part and the high 4 bits [19:16] (TIMER2 / 3) or [31:28] (TIMER1 / 4) for CHxVAL bit-field and CARL bit-field are used for the fractional part. By adjust the CHxVAL or CARL values over 16 consecutive periods (no more than one TIMER clock cycle at a time) in a predefined way, can increase 16-fold in resolution.
Page 715: Figure 23-79. Pwm Adjustment Mode Schematic Diagram
GD32G553 User Manual (23-6) ⁄ PSC_CLK When the adjustment mode is enabled (ADMEN=1), For 16-bit (TIMER2 / 3), (23-7) ( 65535+ 15 16 ⁄ ⁄ PSC_CLK For 32-bit (TIMER1 / 4), (23-8) -1)+ 15 16 ⁄ ⁄ PSC_CLK When the adjustment mode is enabled, the max values of the CHxVAL[19:0] bit-field and...
Page 716: Table 23-14. Chxval Bit-Field Changes In The Center-Aligned Counting Mode
GD32G553 User Manual CHxVAL[19:16] / Period CARL[19:16] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 The PWM adjustment mode can also use in center-aligned counting mode, the details are Table 23-4. CHxVAL and CARL bit-field changes in the center-aligned counting shown in mode.
Page 717: Figure 23-80. Ch0 And Ch2 With Asymmetric Pwm Mode
GD32G553 User Manual determined by a pair of TIMER_CHxCV / TIMER_CH(x+1)CV (or TIMER_CH(x-1)CV) registers with adjacent offset addresses. The TIMER_CHxCV register determines the waveform when counting up, and the TIMER_CH(x+1)CV (or TIMER_CH(x-1)CV) register determines the waveform when counting down. The details are as follows: ...
Page 718: Table 23-15.The Composite Pwm Pulse Width
GD32G553 User Manual by the following table. Table 23-15.The Composite PWM pulse width Condition Mode PWM pulse width (CARL + 0x0001) + PWM mode 0 CHxVAL < CHxCOMVAL_ADD (CHxVAL – CHxCOMVAL_ADD) ≤ CARL PWM mode 1 (CHxCOMVAL_ADD – CHxVAL) PWM mode 0 (CHxVAL - CHxCOMVAL_ADD) CHxCOMVAL_ADD <...
Page 719: Figure 23-81. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32G553 User Manual Figure 23-81. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF...
Page 720: Figure 23-84. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32G553 User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 721: Figure 23-86. Four Channels Outputs In Composite Pwm Mode
GD32G553 User Manual next counter next counter period period If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels. This behavior is useful in the generation of lighting PWM control signals where it is desirable that edges are not coincident with each other pair to help eliminate noise generation.
Page 722: Figure 23-87. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel≠2'B00)
GD32G553 User Manual CHxCOMCTL[3:0] bits;  CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle. CHxOMPSEL = 2’b10, only the counter is counting down, the OxCPRE signal is output ...
Page 723 GD32G553 User Manual is defined by configuring the CHxCOMCTL bit. The OxCPRE signal has several types of output function. The OxCPRE signal type is defined by configuring the CHxCOMCTL bit. These include keeping the original level by configuring the CHxCOMCTL field to 0x00, setting to high by configuring the CHxCOMCTL field to 0x01,...
Page 724: Table 23-16. Examples Of Slave Mode
GD32G553 User Manual Decoder Please refer to Advanced timer (TIMERx, x=0, 7,19) Decoder Quadrature decoder and decoder clock output Please refer to Advanced timer (TIMERx, x=0, 7,19) Quadrature decoder and decoder clock output Index input function Please refer to Advanced timer (TIMERx, x=0, 7,19) Index input function...
Page 725: Figure 23-89. Restart Mode
GD32G553 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Restart mode The counter will be TSCFG3[4:0] For the ITI0, no filter For ITI0, no polarity cleared and restart 5’b00001, and prescaler can be selector can be used.
Page 726: Figure 23-91. Event Mode
GD32G553 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 23-91. Event mode Restart + event mode The counter is reinitialized and started when a rising edge of trigger input comes. Exam4 Pause + restart mode The counter will be reset when a rising edge or falling edge (is configured by PRMRPSEL bit in TIMERx_SMCFG register) of trigger input comes.
Page 727: Figure 23-92. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X60
GD32G553 User Manual Single pulse mode is also applicable to composite PWM mode (CHxCPWMEN = 1’b1 and CHxMS[2:0] = 3’b000). Figure 23-92. Single pulse mode TIMERx_CHxCV = 0x04, TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0] in TIMERx_CHCTLx registers.
Page 728: Figure 23-93. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32G553 User Manual  When counter counting up (DIR = 0 in TIMERx_CTL0 register), the value of TIMERx_CHxCV should be set to 0; When counting down (DIR =1 in TIMERx_CTL0 register), the value of TIMERx_CHxCV should be greater than or equal to the value of TIMERx_CAR register.
Page 729 GD32G553 User Manual When the counter works in center-aligned counting mode, this function can be used to indicates the counter direction of the counter. When the counter works in decoder modes, this function can be used to indicates the rotation direction for the external signal.
Page 730: Registers Definition (Timerx, X=1,2,3,4)
GD32G553 User Manual Registers definition (TIMERx, x=1,2,3,4) 23.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 731 GD32G553 User Manual 0: The shadow register for TIMERx_CAR register is disabled 1: The shadow register for TIMERx_CAR register is enabled CAM[1:0] Counter align mode selection 00: No center-aligned mode (edge-aligned mode). The direction of the counter is specified by the DIR bit.
Page 732 GD32G553 User Manual – The slave mode controller generates an update event. 1: Update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UG bit is set or the slave mode controller generates a hardware reset event.
Page 733 GD32G553 User Manual selects the counter enable signal as TRGO0. The counter enable signal is set when CEN control bit is set or the trigger input in pause mode is high. There is a delay between the trigger input in pause mode and the TRGO0 output, except if the master-slave mode is selected.
Page 734 GD32G553 User Manual 0: Counter is reset at falling edge 1: Counter is reset at rising edge DECMODS Decoder mode update source This bit used to select the decoder mode update source 0: Decoder mode is updated by the TIMER update event after the modification. (Just used when the index signal is disabled.)
Page 735 GD32G553 User Manual signal and the length of the digital filter applied to ETIFP. 0000: Filter disabled. f , N=1. SAMP 0001: f , N=2. SAMP CK_TIMER 0010: f , N=4. SAMP CK_TIMER 0011: f , N=8. SAMP CK_TIMER 0100: f / 2, N=6.
Page 736 GD32G553 User Manual Bits Fields Descriptions CH3COMADDIE Channel 3 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode. CH2COMADDIE Channel 2 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode.
Page 737 GD32G553 User Manual 1: Index interrupt enabled TRGDEN Trigger DMA request enable 0: Disabled 1: Enabled Reserved Must be kept at reset value. CH3DEN Channel 3 capture / compare DMA request enable 0: Disabled 1: Enabled CH2DEN Channel 2 capture / compare DMA request enable...
Page 738 GD32G553 User Manual 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DIRTRANI CH3COM CH2COM CH1COM CH0COM INDERRIF DECDISIF DECJIF...
Page 739 GD32G553 User Manual decoder modes, and cleared by software. 0: No direction transform interrupt occurred 1: Direction transform interrupt occurred DECDISIF Quadrature decoder signal disconnection interrupt flag 0: No quadrature decoder signal disconnection interrupt occurred 1: Quadrature decoder signal disconnection interrupt occurred Note: This bit just used for quadrature decoder signal disconnection detection is enabled (when DECDISDEN =1).
Page 740 GD32G553 User Manual 1: Trigger interrupt occurred Reserved Must be kept at reset value. CH3IF Channel 3 capture / compare interrupt flag Refer to CH0IF description CH2IF Channel 2 capture / compare interrupt flag Refer to CH0IF description CH1IF Channel 1 capture / compare interrupt flag...
Page 741 GD32G553 User Manual Refer to CH0COMADDG description. CH0COMADDG Channel 0 additional compare event generation. This bit is set by software to generate a compare event in channel 0 additional, it is automatically cleared by hardware. When this bit is set, the CH0COMADDIF flag will be set, and the corresponding interrupt will be sent if enabled.
Page 742 GD32G553 User Manual Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1ADDU CH0ADDU CH1COM CH0COM CH1COM CH0COM CH1MS CH0MS ADDSEN ADDSEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
Page 743 GD32G553 User Manual Refer to CH0COMCTL[2:0] description 23:17 Reserved Must be kept at reset value. CH0COMCTL[3] Channel 0 compare output control Refer to CH0COMCTL[2:0] description CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 744 GD32G553 User Manual compare register TIMERx_CH0CV. 0100: Force low. O0CPRE is forced low level. 0101: Force high. O0CPRE is forced high level. 0110: PWM mode 0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV, otherwise it is inactive. When counting down, O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV, otherwise it is active.
Page 745 GD32G553 User Manual When this bit is set, the effect of an event on the trigger in input on the capture / compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison.
Page 746 GD32G553 User Manual 0010: f , N=4. SAMP CK_TIMER 0011: f , N=8. SAMP CK_TIMER 0100: f / 2, N=6. SAMP 0101: f / 2, N=8. SAMP 0110: f / 4, N=6. SAMP 0111: f / 4, N=8. SAMP 1000: f / 8, N=6.
Page 747 GD32G553 User Manual Refer to CH3MS[1:0]description. CH2MS[2] Channel 2 I / O mode selection Refer to CH2MS[1:0] description. CH3COMADDSEN Channel 3 additional compare output shadow enable Refer to CH2COMADDSEN description. CH2COMADDSEN Channel 2 additional compare output shadow enable When this bit is set, the shadow register of TIMERx_CH2COMV_ADD register which updates at each update event will be enabled.
Page 748 GD32G553 User Manual bit in TIMERx_CHCTL2 register is reset). 00: Channel 3 is configured as output. 01: Channel 3 is configured as input, IS3 is connected to CI3FE3. 10: Channel 3 is configured as input, IS3 is connected to CI2FE3.
Page 749 GD32G553 User Manual When counting down, the O2CPRE is active. When a trigger event occurs, the O2CPRE is inactive. The O2CPRE is active again at the next update event. 1010: Programmable pulse output. A programmable pulse output on the CH2_O when the counter matches the output compare register TIMERx_CH2CV.
Page 750 GD32G553 User Manual bit in TIMERx_CHCTL2 register is reset). 00: Channel 2 is configured as output. 01: Channel 2 is configured as input, IS2 is connected to CI2FE2. 10: Channel 2 is configured as input, IS2 is connected to CI3FE2.
Page 751 GD32G553 User Manual 1111: f / 32, N=8. SAMP CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is cleared. 00: Prescaler disabled, capture is done on each channel input edge.
Page 752 GD32G553 User Manual Refer to CH0EN description CH1NP Channel 1 complementary capture / compare polarity Refer to CH0NP description. Reserved Must be kept at reset value. CH1P Channel 1 capture / compare function polarity Refer to CH0P description CH1EN Channel 1 capture / compare function enable...
Page 753 GD32G553 User Manual Counter register (TIMERx_CNT) (TIMERx, x= 2,3) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). UPIFBU Reserved CNT[15:0] Bits Fields Descriptions UPIFBU UPIF bit backup This bit is a backup of UPIF bit in TIMERx_INTF register and read-only. This bit is only valid when UPIFBUEN = 1.
Page 754 GD32G553 User Manual When the PWMADMEN =0, this bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter. When the PWMADMEN =1, this bit-field just indicates the integer part of the counter value, and without the fractional part.
Page 755 GD32G553 User Manual This register has to be accessed by word (32-bit). CARL[19:16] Reserved CARL[15:0] Bits Fields Descriptions 31:28 CARL[19:16] Counter auto reload value (bit 16 to 19) When the PWMADMEN =0, CARL[19:16] bit-field is 0000. When the PWMADMEN =1, CARL[19:16] bit-field specifies fractional part of the auto reload value.
Page 756 GD32G553 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH0VAL[19:16] Reserved CH0VAL[15:0] Bits Fields Descriptions 31:28 CH0VAL[19:16] Capture / compare value of channel 0 (bit 16 to 19) When channel 0 is configured in input mode, CH0VAL[19:16] bit-field is 0000.
Page 757 GD32G553 User Manual 31:0 CH0VAL[31:0] Capture / compare value of channel 0 When channel 0 is configured in input mode, CH0VAL[31:28] bit-field is 0000, CH0VAL[27:0] bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 758 GD32G553 User Manual compare value. Channel 1 capture / compare value register (TIMERx_CH1CV) (TIMERx, x= 1,4) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1VAL[31:16] CH1VAL[15:0] Bits Fields Descriptions 31:0 CH1VAL[31:0] Capture / compare value of channel 1 When channel 1 is configured in input mode, CH1VAL[31:28] bit-field is 0000, CH1VAL[27:0] bit-field indicates the counter value at the last capture event.
Page 759 GD32G553 User Manual When channel 2 is configured in input mode, CH2VAL[19:16] bit-field is 0000. When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 760 GD32G553 User Manual value. Channel 3 capture / compare value register (TIMERx_CH3CV) (TIMERx, x= 2,3) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3VAL[19:16] Reserved CH3VAL[15:0] Bits Fields Descriptions 31:28 CH3VAL[19:16] Capture / compare value of channel 3 (bit 16 to 19) When channel 3 is configured in input mode, CH3VAL[19:16] bit-field is 0000.
Page 761 GD32G553 User Manual CH3VAL[15:0] Bits Fields Descriptions 31:0 CH3VAL[31:0] Capture / compare value of channel 3 When channel 0 is configured in input mode, CH3VAL[31:28] bit-field is 0000, CH3VAL[27:0] bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 762 GD32G553 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1COMVAL_ADD[31:16] CH1COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 CH1COMVAL_ADD Additional compare value of channel 1 (bit 16 to 31) [31:16] This bit-field only for TIMER1 / 4.
Page 763 GD32G553 User Manual Channel 3 additional compare value register (TIMERx_CH3COMV_ADD) Address offset: 0x70 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COMVAL_ADD[31:16] CH3COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 CH3COMVAL_ADD Additional compare value of channel 3 (bit 16 to 31) [31:16] This bit-field only for TIMER1 / 4.
Page 764 GD32G553 User Manual CH1CPWMEN Channel 1 composite PWM mode enable 0: Disabled 1: Enabled CH0CPWMEN Channel 0 composite PWM mode enable 0: Disabled 1: Enabled 27:20 Reserved Must be kept at reset value. DECDISDEN Quadrature decoder signal disconnection detection enable...
Page 765 GD32G553 User Manual 11:10 CH1OMPSEL[1:0] Channel 1 output match pulse select When the match events occur, this bit is used to select the output of O1CPRE which drives CH1_O. 00: The O1CPRE signal is output normal with the configuration of CH1COMCTL [2:0] bits.
Page 766 GD32G553 User Manual 000: OCPRE_CLR0 001: OCPRE_CLR1 … 111: OCPRE_CLR7 OCPRE_CLR inputs selection TIMER1 / 2 TIMER3 / 4 保留 OCPRE_CLR0 CMP0_OUT 保留 OCPRE_CLR1 CMP1_OUT 保留 OCPRE_CLR2 CMP2_OUT 保留 OCPRE_CLR3 CMP3_OUT 保留 OCPRE_CLR4 CMP4_OUT 保留 OCPRE_CLR5 CMP5_OUT 保留 OCPRE_CLR6 CMP6_OUT 保留...
Page 767 GD32G553 User Manual Reserved OPPSC[2:0] OPWID[7:0] INDRSTE INDP[1:0] FINDRST Reserved INDRSTDIR[1:0] Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. 26:24 OPPSC[2:0] Output pulse prescaler This bit-field specifies the clock prescaler for the pulse generator. (OPPSC [2:0]) = (2...
Page 768 GD32G553 User Manual Note: The INDRSTDIR[1:0] bit-field can be modified only when INDRSTEN =0. INDRSTEN Index signal reset enable 0: Index signal resets the counter disabled 1: Index signal resets the counter enabled DMA configuration register (TIMERx_DMACFG) Address offset: 0xE0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 769 GD32G553 User Manual This register has to be accessed by word (32-bit). DMATB[31:16] DMATB[15:0] Bits Fields Descriptions 31:0 DMATB[31:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address ranges from (start address) to (start address + transfer count * 4) will be accessed.
Page 770: General Level3 Timer (Timerx, X=14)
GD32G553 User Manual 23.3. General level3 timer (TIMERx, x=14) Overview 23.3.1. The general level3 timer module (TIMER14) is a three-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 771: Function Overview
GD32G553 User Manual configuration of the general level3 timer. Figure 23-94. General level3 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TIMERx_TRGO0 Trigger selector CH0_I Input Logic Synchronizer & Filter Edge selector Prescaler CH1_I & Edge Detector TIMERx_CHxCV/ Counter TIMERx_MCHxCV PSC_CLK TIMER_CK DMA REQ/ACK...
Page 772: Figure 23-95. Normal Mode, Internal Clock Divided By 1
GD32G553 User Manual Figure 23-95. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 TSCFG6[4:0] are setting to a nonzero value (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of...
Page 773: Figure 23-96. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32G553 User Manual Figure 23-96. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 774 GD32G553 User Manual the counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Timing diagram of up counting mode, PSC=0 / 2 Figure 23-97. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2...
Page 775: Figure 23-98. Timing Diagram Of Up Counting Mode, Change Timerx_Car On The Go
GD32G553 User Manual Timing diagram of up counting mode, Figure 23-98. change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR value ARSE = 1 CNT_REG...
Page 776: Figure 23-99. Repetition Timechart For Up-Counter
GD32G553 User Manual Figure 23-99. Repetition timechart for up-counter TIMER_CK CNT_CLK 61 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 CNT_REG 62 63 00 01 Underflow Overflow TIMERx_CREP0 = 0x0...
Page 777: Figure 23-100. Input Capture Logic For Channel 0
GD32G553 User Manual Figure 23-100. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture CI1FE0 Clock Register Prescaler Prescaler MCI0FE0 （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channals Figure 23-101.
Page 778: Output Compare Mode
GD32G553 User Manual Based on the input signal and quality of requested signal, configure compatible CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits.
Page 779: Figure 23-102. Output Compare Logic (When Mchxmsel = 2'B00, X=0)
GD32G553 User Manual Figure 23-102. Output compare logic (when MCHxMSEL = 2’b00, x=0) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control polarity selector MCHxCV CHxCOMCTL/ CHxP,CHxEN/ CNT<CHxCV/ MCHx_O MCHxCOMCTL MCHxFP,MCHxEN MCHxCV Counter Figure 23-103. Output compare logic (when MCHxMSEL = 2’b11, x=0) Figure 23-104.
Page 780: Figure 23-105. Output-Compare In Three Modes
GD32G553 User Manual output level of CHx_O / MCHx_O depends on OxCPRE signal, CHxP / MCHxP bits and CHxEN / MCHxEN bits. Please refer to Figure 23-103. Output compare logic (when MCHxMSEL = 2’b11, x=0). For examples (the MCHx_O output is independent from the CHx_O output):...
Page 781: Figure 23-106. Pwm Mode Timechart
GD32G553 User Manual Figure 23-105. Output-compare in three modes CNT_CLK CNT_REG 03 04 03 04 03 04 Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL / MCHxCOMCTL bit to 4’b0110 (PWM mode 0) or to 4’b0111(PWM mode 1)), the channel can generate PWM waveform according...
Page 782: Figure 23-107. Adjustment Mode: Data Format And The Register Bit-Field
GD32G553 User Manual Figure 23-106. PWM mode timechart CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CHxIF CHxOF Adjustment mode Adjustment mode is enabled by setting ADMEN bit in TIMERx_CTL0 register to 1, and this mode can improve the effective resolution of the output PWM wave. The duty cycle resolution can be improved by the CHxVAL[19:0] bit-field in the TIMERx_CHxCV register, and the PWM frequency resolution can be improved by the CARL[19:0] bit-field in the TIMERx CAR register.
Page 783: Figure 23-108. Pwm Adjustment Mode Schematic Diagram
GD32G553 User Manual 8. ADMEN bit must be cleared; 9. CHxIF bit must be cleared; 10. Set the CEN bit to 1. The following formula to calculate the PWM Resolution: (23-9) Resolution = f ⁄ PSC_CLK According to Equation (23-9), when the adjustment mode is disabled (ADMEN=0), the PWM...
Page 784: Table 23-18.The Composite Pwm Pulse Width
GD32G553 User Manual CHxVAL[19:16] / Period CARL[19:16] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Composite PWM mode In the Composite PWM mode (CHxCPWMEN = 1’b1, CHxMS[2:0] = 3’b000 and CHxCOMCTL = 4’b0110 or 4’b0111), the PWM signal output in channel x (x=0, 1) is composited by CHxVAL and CHxCOMVAL_ADD bits.
Page 785: Figure 23-109. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32G553 User Manual Condition Mode PWM pulse width counting) PWM mode 0(up counting) or PWM mode 1(down counting) CHxCOMVAL_ADD > CARL > PWM mode 0(down CHxVAL counting) or 100% PWM mode 1(up counting) (CHxVAL>CARL) and The output of CHx_O is keeping (CHxCOMVAL_ADD >...
Page 786: Figure 23-110. Channel X Output Pwm With (Chxval = Chxcomval_Add)
GD32G553 User Manual between 0 and CARL. Figure 23-110. Channel x output PWM with (CHxVAL = CHxCOMVAL_ADD) CARL CARL CHxVAL = CHxCOMVAL_ADD CHxVAL = CHxCOMVAL_ADD Constant “0” Constant “0” PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE Constant “1” Constant “1”...
Page 787: Figure 23-113. Channel X Output Pwm Duty Cycle Changing With Chxcomval_Add
GD32G553 User Manual CHxCOMVAL_ADD CHxVAL CARL CARL CHxCOMVAL_ADD CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF The composite PWM mode is intended to support the generation of PWM signals where the period is not modified while the signal is being generated, but the duty cycle will be varied.
Page 788: Figure 23-114. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel =2'B00)
GD32G553 User Manual of OxCPRE which drives CHx_O:  CHxOMPSEL = 2’b00, the OxCPRE signal is output normally with the configuration of CHxCOMCTL[3:0] bits;  CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.
Page 789: Table 23-19. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32G553 User Manual Another special function of the OxCPRE signal is forced output which can be achieved by configuring the CHxCOMCTL field to 0x04 / 0x05. The output can be forced to an inactive / active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV.
Page 790 GD32G553 User Manual Complementary Parameters Output Status POEN ROS CHxEN MCHxEN CHx_O MCHx_O = CHxP, MCHx_O = CHxNP; If the clock for deadtime generator is present, after a deadtime: CHx_O = ISOx, MCHx_O = ISOxN. CHx_O/ MCHx_O output “off-state”: the CHx_O/ MCHx_O output inactive level firstly: CHx_O = CHxP, MCHx_O = CHxNP;...
Page 791: Figure 23-115. Complementary Output With Dead-Time Insertion
GD32G553 User Manual The dead time delay insertion ensures that two complementary signals are not active at the same time. When the channel x match event (TIMERx_CNT = CHxVAL) occurs, OxCPRE will be toggled Figure 23-115. Complementary output with dead-time in PWM mode 0.
Page 792: Figure 23-116. Complementary Output With Different Dead Time(Dtdifen=1)
GD32G553 User Manual Figure 23-116. Complementary output with different dead time(DTDIFEN=1) CARL CHxVAL OxCPRE CHx_O MCHx_O DTFCFG[7:0] DTCFG[7:0] Falling edge Rising edge Break function The MCHx_O output is the inverse of the CHx_O output when the MCHxMSEL=2’b11 (and the MCHxOMCTL bits are not used in the generation of the MCHx_O output). In this case, CHx_O and MCHx_O signals cannot be set to active level at the same time.
Page 793: Figure 23-117. Break0 Function Logic Diagram
GD32G553 User Manual Figure 23-117. BREAK0 function logic diagram CKM clock monitor LVD lock event LOCKUP_LOCK event BRK0G SRAM parity error event Flash ECC error BRKINx pins BRK0INEN BRK0EN Output （x=0..2） BRK0INP Logic CMPx_OUT BRK0CMPxEN （x=0..3） BRK0CMPxP Digital Filter BRK0CMPxEN CMPx_OUT （x=4..7）...
Page 794: Table 23-20. Break Function Input Pins Locked / Released Conditions
GD32G553 User Manual Locked break function The BRKIN0 input pin of general timer have the locked break function, this function can be enabled by setting the BRK0LK bit in the TIMERx_CCHP0 register. When the locked break function is enabled, the BRKIN0 pins need to be configured to open- drain output mode with low level active (BRK0P=0 and BRK0IN0P=0).
Page 795: Figure 23-119. Brkin0 Pin Logic With Break0 Function
GD32G553 User Manual Figure 23-119. BRKIN0 pin logic with BREAK0 function CKM clock monitor LVD lock event LOCKUP_LOCK event SYSBIF BRK0G SRAM parity error event System source Flash ECC error requests BRK0EN HPDF_OUT BRK0HPDFEN Output Logic BRK0CMPxEN CMPx_OUT （x=0..3） BRK0CMPxP...
Page 796: Figure 23-120. Restart Mode
GD32G553 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Restart mode The counter can TSCFG3[4:0] For ITI0, no polarity For the ITI0, no filter and clear 5’b00001, ITI0 is the selector prescaler can be used. restart when selection.
Page 797: Figure 23-122. Event Mode
GD32G553 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 23-122. Event mode Restart + event mode Exam4 The counter is reinitialized and started when a rising edge of trigger input comes. Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0.
Page 798: Figure 23-123. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32G553 User Manual Figure 23-123. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0]/ MCHxCOMCTL[3:0] in TIMERx_CHCTLx/ TIMERx_MCHCTLx registers. In this mode, the pulse width of OxCPRE/ MOxCPRE signal is determined by the TIMERx_CAR register.
Page 799: Figure 23-124. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32G553 User Manual TIMERx_CHxCV/ TIMERx_MCHxCV should be set to 0; When counting down (DIR =1 in TIMERx_CTL0 register), the value of TIMERx_CHxCV/ TIMERx_MCHxCV should be greater than or equal to the value of TIMERx_CAR register. Figure 23-124. delayable single pulse mode TIMERx_CHxCV=0x00, TIMERx_CAR=0x60...
Page 800 GD32G553 User Manual Timer debug mode When the Cortex -M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 ® register set to 1, the TIMERx counter stops.
Page 801: Register Definition (Timerx, X=14)
GD32G553 User Manual Register definition (TIMERx, x=14) 23.3.5. TIMER14 base address: 0x4001 4000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved UPIFBUE Reserved ADMEN Reserved CKDIV[1:0] ARSE...
Page 802 GD32G553 User Manual 0: Single pulse mode is disabled. Counter continues after an update event. 1: Single pulse mode is enabled. The CEN bit is cleared by hardware and the counter stops at next update event. Update source This bit is used to select the update event sources by software.
Page 803 GD32G553 User Manual Refer to CCUC [0] description. 29:11 Reserved Must be kept at reset value. ISO1 Idle state of channel 1 output Refer to ISO0 bit ISO0N Idle state of multi mode channel 0 complementary output 0: When POEN bit is reset, MCH0_O is set low.
Page 804 GD32G553 User Manual CCUC[0] Commutation control shadow register update control The CCUC[2:1] and CCUC[0] field are used to control the commutation control shadow register update. When the commutation control shadow registers (for CHxEN, MCHxEN and CHxCOMCTL bits) are enabled (CCSE=1), the update control of the shadow registers with the CCUC[2:0] bit-field are shown as below: 000: The shadow registers update when CMTG bit is set.
Page 805 GD32G553 User Manual 25:8 Reserved Must be kept at reset value. Master-slave mode This bit can be used to synchronize the selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected.
Page 806 GD32G553 User Manual MCH0IE Multi mode channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MMCH0SEL[1:0] = 2’b00). 19:15 Reserved Must be kept at reset value. TRGDEN...
Page 807 GD32G553 User Manual 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1COM CH0COM Reserved Reserved MCH0OF Reserved MCH0IF...
Page 808 GD32G553 User Manual If multi mode channel 0 is in output mode, this flag is set when a compare event occurs. If multi mode channel 0 is set to input mode, this bit will be reset by reading TIMERx_MCH0CV. 0: No multi mode channel 0 capture/compare interrupt occurred...
Page 809 GD32G553 User Manual 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV. 0: No channel 0 interrupt occurred 1: Channel 0 interrupt occurred...
Page 810 GD32G553 User Manual value of the counter is captured to TIMERx_MCH0CV register, and the MCH0OF flag is set if the MCH0IF flag has been set. 0: No generate a multi mode channel 0 capture or compare event 1: Generate a multi mode channel 0 capture or compare event...
Page 811 GD32G553 User Manual 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1ADDU CH0ADDU CH1COM CH0COM CH1COM...
Page 812 GD32G553 User Manual 0: TIMERx_CH0COMV_ADD register is updated when an update event occurs. 1: TIMERx_CH0COMV_ADD register is updated when the counter matches the value of CH0VAL. Reserved Must be kept at reset value. CH1COMCTL[3] Channel 1 compare output control Refer to CH0COMCTL[2:0] description...
Page 813 GD32G553 User Manual level of CH0_O depends on CH0P bit. Note: When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2’b11, This bit-field controls the behavior of O0CPRE which drives CH0_O and MCH0_O. The active level of O0CPRE is high, while the active level of CH0_O and MCH0_O depends on CH0P and MCH0P bits.
Page 814 GD32G553 User Manual This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP0 register is 11 and CH0MS bit-field is 000 (compare mode). CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register which updates at each update event will be enabled.
Page 815 GD32G553 User Manual Same as output compare mode. 29:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description. 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description. CH1MS[1:0] Channel 1 I/O mode selection Same as output compare mode.
Page 816 GD32G553 User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved MCH1P Reserved CH1P CH1EN MCH0P MCH0EN CH0P CH0EN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 817 GD32G553 User Manual 1: Channel 0 active low When channel 0 is configured in input mode, these bits specifie the channel 0 input signal’s polarity. [MCH0P, CH0P] will select the active trigger or capture polarity for channel 0 input signals.
Page 818 GD32G553 User Manual When the PWMADMEN =1, this bit-field just indicates the integer part of the counter value, and without the fractional part. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 819 GD32G553 User Manual 15:0 CARL[15:0] Counter auto reload value When the PWMADMEN =0, CARL[15:0] bit-field specifies the auto reload value of the counter. When the PWMADMEN =1, CARL[15:0] bit-field specifies integer part of the auto reload value. Counter repetition register 0 (TIMERx_CREP0)
Page 820 GD32G553 User Manual When channel 0 is configured in input mode, CH0VAL[19:16] bit-field is 0000. When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 821 GD32G553 User Manual counter value at the last capture event. And this bit-field is read-only. When channel 1 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 822 GD32G553 User Manual 25:20 Reserved Must be kept at reset value. 19:16 BRK0F[3:0] BREAK0 input signal filter An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample BREAK0 input signal and the length of the digital filter applied to BREAK0.
Page 823 GD32G553 User Manual This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK0EN BREAK0 input signal enable This bit can be set to enable the BREAK0 input signal 0: BREAK0 input disabled 1: BREAK0 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 824 GD32G553 User Manual This bit-field can be written only once after the system reset. Once the TIMERx_CCHP0 register has been written, this bit-field will be writing protected. DTCFG[7:0] Dead time configuration This bit-field controls the value of the dead-time, which is inserted before the output transitions.
Page 825 GD32G553 User Manual ETIFP input. 0: Multi mode channel 0 output compare clear disabled. 1: Multi mode channel 0 output compare clear enabled. MCH0COMCTL Multi mode channel 0 output compare control [2:0] When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2’b00, the MCH0COMCTL[3] and MCH0COMCTL[2:0] bit-field control the...
Page 826 GD32G553 User Manual If configured in PWM mode, the MO0CPRE level changes only when the output compare mode switches from “Timing” mode to “PWM” mode or the result of the comparison changes. When the outputs of CH0 and MCH0 are complementary, this bit-field is preloaded.
Page 827 GD32G553 User Manual Reserved Must be kept at reset value. MCH0MS[2] Multi mode channel 0 I/O mode selection Refer to MCH0MS[1:0] description. 29:8 Reserved Must be kept at reset value. MCH0CAPFLT[3:0] Multi mode channel 0 input capture filter control. An event counter is used in the digital filter, in which a transition on the output occurs after N input events.
Page 828 GD32G553 User Manual Reserved Reserved MCH0FP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. MCH0FP[1:0] Multi mode channel 0 capture/compare free polarity When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2’b00, these bits specific the multi mode channel 0 output signal polarity.
Page 829 GD32G553 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 MCH0VAL[15:0] Capture/compare value of multi mode channel 0. When multi mode channel 0 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 830 GD32G553 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1COMVAL_ADD Additional compare value of channel 1 [15:0] When channel 1 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 831 GD32G553 User Manual 11:10 CH1OMPSEL[1:0] Channel 1 output match pulse select When the match events occur, this bit is used to select the output of O1CPRE which drives CH1_O. 00: The O1CPRE signal is output normal with the configuration of CH1COMCTL[2:0] bits.
Page 832 GD32G553 User Manual 1: CMP3 input signal will be inverted (BRK0P=0, the input signal is active high; BRK0P =1, the input signal is active low) This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK0CMP2P...
Page 833 GD32G553 User Manual BRK0CMP6EN BREAK0 CMP6 enable 0: CMP6 input disabled 1: CMP6 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK0CMP5EN BREAK0 CMP5 enable 0: CMP5 input disabled 1: CMP5 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00.
Page 834 GD32G553 User Manual BRK0CMP7EN BREAK0 CMP7 enable 0: CMP7 input disabled 1: CMP7 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. Reserved Must be kept at reset value. BRK0IN0EN BREAK0 BRKIN0 alternate function input enable...
Page 835 GD32G553 User Manual is 00. 18:0 Reserved must be kept at reset value Counter repetition register 1 (TIMERx_CREP1) Address offset: 0x98 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CREP1[31:16] CREP1[15:0] Bits Fields Descriptions 31:0...
Page 836 GD32G553 User Manual 1: Dead time value modified on-the-fly enable This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP0 register is 00. DTDIFEN Dead time configure different enable 0: The dead time for both rising and falling edges are same, which is defined in DTCFG[7:0] bit-field in TIMERx_CCHP1 register.
Page 837 GD32G553 User Manual 6’b000001: transfer 2 times … 6’b111000: transfer 57 times Reserved Must be kept at reset value. DMATA[5:0] DMA transfer access start address This field defines the start address of accessing the TIMERx_DMATB register by DMA. When the first access to the TIMERx_DMATB register is done, this bit-field specifies the address just accessed.
Page 838 GD32G553 User Manual CCUSEL CREPSEL CHVSEL OUTSEL Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CCUSEL Commutation control shadow register update select This bit is valid only when the CCUC[2:0] bit-field are set to 100. 0: The shadow registers update when the counter generates an overflow/ underflow event.
Page 839: Figure 23-125. General Level4 Timer Block Diagram
GD32G553 User Manual 23.4. General level4 timer (TIMERx, x=15, 16) Overview 23.4.1. The general level4 timer module (TIMER15 / 16) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 840 GD32G553 User Manual Figure 23-125. General level4 timer block diagram Input Logic Synchronizer&Filter Edge selector Prescaler CH0_I &Edge Detector MCH0_I TIMERx_CHxCV/ CK_TIMER Counter TIMERx_MCHxCV PSC_CLK Counter Control TIMER_CK DMA REQ/ACK DMA controller TIMERx_CH0 TIMERx_UP req en/direct req set Register /Interrupt...
Page 841: Figure 23-126. Normal Mode, Internal Clock Divided By 1
GD32G553 User Manual Figure 23-126. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor between 1 and 65536.
Page 842: Figure 23-128. Timing Diagram Of Up Counting Mode, Psc=0/2
GD32G553 User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. If the repetition counter is set, the update events will be generated after (TIMERx_CREP0/1+1) times of overflow.
Page 843: Figure 23-129. Timing Diagram Of Up Counting Mode, Change Timerx_Car On The Go
GD32G553 User Manual Timing diagram of up counting mode, Figure 23-129. change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR value ARSE = 1 CNT_REG...
Page 844: Figure 23-130. Repetition Timechart For Up-Counter
GD32G553 User Manual Figure 23-130. Repetition timechart for up-counter TIMER_CK CNT_CLK 61 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 CNT_REG 62 63 00 01 Underflow Overflow TIMERx_CREP0 = 0x0...
Page 845: Figure 23-131. Input Capture Logic For Channel 0
GD32G553 User Manual Figure 23-131. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Filter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock Counter Register MCI0FE0 Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channals Figure 23-132.
Page 846: Figure 23-133. Output Compare Logic (When Mchxmsel = 2'B00, X=0)
GD32G553 User Manual Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits. Step3: Capture source selection (CHxMS bit in TIMERx_CHCTL0 register, MCHxMS bit in TIMERx_MCHCTL0 register).
Page 847: Figure 23-134. Output Compare Logic (When Mchxmsel = 2'B11, X=0)
GD32G553 User Manual Figure 23-134. Output compare logic (when MCHxMSEL = 2’b11, x=0) The relationship between the channel output signal CHx_O/MCHx_O and the OxCPRE/ Channel output prepare signal) is described as MOxCPRE signal (more details refer to blew(the active level of OxCPRE is high and the active level of MOxCPRE is high).
Page 848: Figure 23-135. Output-Compare In Three Modes
GD32G553 User Manual output can be set, cleared, or toggled based on CHxCOMCTL/ MCHxCOMCTL. When the counter reaches the value in the TIMERx_CHxCV/ TIMERx_MCHxCV register, the CHxIF/ MCHxIF bit will be set and the channel (n) interrupt is generated if CHxIE/ MCHxIE = 1. And the DMA request will be asserted, if CHxDEN/ MCHxDEN =1.
Page 849: Figure 23-136. Pwm Mode Timechart
GD32G553 User Manual to the TIMERx_CAR registers and TIMERx_CHxCV/ TIMERx_MCHxCV registers. The EAPWM’s period is determined by TIMERx_CAR and the duty cycle is determined by Figure 23-136. PWM mode timechart TIMERx_CHxCV/ TIMERx_MCHxCV. shows the EAPWM output and interrupts waveform. In up counting mode, if the value of TIMERx_CHxCV/ TIMERx_MCHxCV is greater than the value of TIMERx_CAR, the output will be always active in PWM mode 0 (CHxCOMCTL/ MCHxCOMCTL =4’b0110).
Page 850: Table 23-22. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32G553 User Manual by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0/ PWM mode 1 output is another output type of OxCPRE which is setup by configuring the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 851 GD32G553 User Manual Complementary Parameters Output Status POEN ROS CHxEN MCHxEN CHx_O MCHx_O CHxP, MCHx_O = CHxNP; If the clock for deadtime generator is present, after a deadtime: CHx_O = ISOx, MCHx_O = ISOxN. CHx_O/ MCHx_O output “off-state”: the CHx_O/ MCHx_O output inactive level firstly: CHx_O = CHxP, MCHx_O = CHxNP;...
Page 852: Figure 23-137. Complementary Output With Dead-Time Insertion
GD32G553 User Manual The dead time delay insertion ensures that two complementary signals are not active at the same time. When the channel x match event (TIMERx_CNT = CHxVAL) occurs, OxCPRE will be toggled Figure 23-137. Complementary output with dead-time in PWM mode 0.
Page 853: Figure 23-138. Complementary Output With Different Dead Time(Dtdifen=1)
GD32G553 User Manual Figure 23-138. Complementary output with different dead time(DTDIFEN=1) CARL CHxVAL OxCPRE CHx_O MCHx_O DTFCFG[7:0] DTCFG[7:0] Falling edge Rising edge Break function The MCHx_O output is the inverse of the CHx_O output when the MCHxMSEL=2’b11 (and the MCHxOMCTL bits are not used in the generation of the MCHx_O output). In this case, CHx_O and MCHx_O signals cannot be set to active level at the same time.
Page 854: Figure 23-139. Break0 Function Logic Diagram
GD32G553 User Manual Figure 23-139. BREAK0 function logic diagram CKM clock monitor LVD lock event LOCKUP_LOCK event BRK0G SRAM parity error event Flash ECC error BRKINx pins BRK0INEN BRK0EN Output （x=0..2） BRK0INP Logic CMPx_OUT BRK0CMPxEN （x=0..3） BRK0CMPxP Digital Filter BRK0CMPxEN CMPx_OUT （x=4..7）...
Page 855: Table 23-23. Break Function Input Pins Locked/ Released Conditions
GD32G553 User Manual Locked break function The BRKIN0 input pin of general timer have the locked break function, this function can be enabled by setting the BRK0LK bit in the TIMERx_CCHP0 register. When the locked break function is enabled, the BRKIN0 pins need to be configured to open- drain output mode with low level active (BRK0P=0 and BRK0IN0P=0).
Page 856: Figure 23-141. Brkin0 Pin Logic With Break0 Function
GD32G553 User Manual Figure 23-141. BRKIN0 pin logic with BREAK0 function CKM clock monitor LVD lock event LOCKUP_LOCK event SYSBIF BRK0G SRAM parity error event System source Flash ECC error requests BRK0EN HPDF_OUT BRK0HPDFEN Output Logic BRK0CMPxEN CMPx_OUT （x=0..3） BRK0CMPxP...
Page 857 GD32G553 User Manual Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event. When the interrupt event was asserted, TIMERx will send a request to DMA, which is configured to M2P mode and PADDR is TIMERx_DMATB, then DMA will access the TIMERx_DMATB.
Page 858 GD32G553 User Manual Register definition (TIMERx, x=15, 16) 23.4.5. TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved...
Page 859 GD32G553 User Manual Reserved Must be kept at reset value. Single pulse mode 0: Single pulse mode is disabled. Counter continues after an update event. 1: Single pulse mode is enabled. The CEN bit is cleared by hardware and the counter stops at next update event.
Page 860 GD32G553 User Manual Bits Fields Descriptions 31:30 CCUC[2:1] Commutation control shadow register update control Refer to CCUC [0] description. 29:10 Reserved Must be kept at reset value. ISO0N Idle state of multi mode channel 0 complementary output 0: When POEN bit is reset, MCH0_O is set low.
Page 861 GD32G553 User Manual DMA and interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). MCH0 Reserved Reserved MCH0IE Reserved Reserved CH0DEN UPDEN BRKIE Reserved CMTIE Reserved CH0IE UPIE Bits...
Page 862 GD32G553 User Manual 1: Enabled Reserved Must be kept at reset value. CH0IE Channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 863 GD32G553 User Manual 19:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software.
Page 864 GD32G553 User Manual Reserved BRK0G Reserved CMTG Reserved CH0G Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. MCH0G Multi mode channel 0 capture or compare event generation. This bit is set by software to generate a capture or compare event in multi mode channel 0, it is automatically cleared by hardware.
Page 865 GD32G553 User Manual 1: Generate a channel 0 capture or compare event Update event generation This bit can be set by software, and automatically cleared by hardware. When this bit is set, the counter is cleared if the up counting mode is selected. The prescaler counter is cleared at the same time.
Page 866 GD32G553 User Manual O0CPRE which drives CH0_O. The active level of O0CPRE is high, while the active level of CH0_O depends on CH0P bit. Note: When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2’b11, This bit-field controls the behavior of O0CPRE which drives CH0_O and MCH0_O.
Page 867 GD32G553 User Manual Reserved Must be kept at reset value. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. The CH0MS[2:0] bit-field is writable only when the channel is not active (When MCH0MSEL[1:0] = 2’b00, the CH1EN bit in TIMERx_CHCTL2 register is reset;...
Page 868 GD32G553 User Manual This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is cleared. 00: Prescaler disabled, capture is done on each channel input edge. 01: Capture is done every 2 channel input edges.
Page 869 GD32G553 User Manual 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, these bits specifie the channel 0 input signal’s polarity. [MCH0P, CH0P] will select the active trigger or capture polarity for channel 0 input signals.
Page 870 GD32G553 User Manual to this bit-field can change the value of the counter. When the PWMADMEN =1, this bit-field just indicates the integer part of the counter value, and without the fractional part. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 871 GD32G553 User Manual 27:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value (bit 0 to 15) When the PWMADMEN =0, CARL[15:0] bit-field specifies the auto reload value of the counter. When the PWMADMEN =1, CARL[15:0] bit-field specifies integer part of the auto reload value.
Page 872 GD32G553 User Manual 31:28 CH0VAL[19:16] Capture/compare value of channel 0 (bit 16 to 19) When channel 0 is configured in input mode, CH0VAL[19:16] bit-field is 0000. When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 873 GD32G553 User Manual is 00. Note: Every write operation to this bit needs a delay of 1 APB clock to active. Reserved Must be kept at reset value. BRK0REL BREAK0 input released This bit is cleared by hardware when the break input is invalid.
Page 874 GD32G553 User Manual OAEN Output automatic enable This bit specifies whether the POEN bit can be set automatically by hardware. 0: POEN cannot be set by hardware. 1: POEN can be set by hardware automatically at the next update event, if the break input is not active.
Page 875 GD32G553 User Manual This bit-field specifies the write protection property of registers. 00: Protect disabled. No write protection. 01: PROT mode 0. The ISOx/ISOxN bits in TIMERx_CTL1 register, the BRK0EN/ BRK0P/OAEN/DTCFG bits in TIMERx_CCHP0 register are writing protected. 10: PROT mode 1. In addition to the registers in PROT mode 0, the CHxP/MCHxP bits in TIMERx_CHCTL2 register (if related channel is configured in output mode), the ROS/IOS bits in TIMERx_CCHP0 register are writing protected.
Page 876 GD32G553 User Manual Reserved Must be kept at reset value. MCH0MS[2] Multi mode channel 0 I/O mode selection Refer to MCH0MS[1:0] description. 29:17 Reserved Must be kept at reset value. MCH0COMCTL Multi mode channel 0 compare output control. Refer to MCH0COMCTL[2:0] description.
Page 877 GD32G553 User Manual If configured in PWM mode, the MO0CPRE level changes only when the output compare mode switches from “Timing” mode to “PWM” mode or the result of the comparison changes. When the outputs of CH0 and MCH0 are complementary, this bit-field is preloaded.
Page 878 GD32G553 User Manual Refer to MCH0MS[1:0] description. 29:8 Reserved Must be kept at reset value. MCH0CAPFLT[3:0] Multi mode channel 0 input capture filter control. An event counter is used in the digital filter, in which a transition on the output occurs after N input events.
Page 879 GD32G553 User Manual Reserved MCH0FP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. MCH0FP[1:0] Multi mode channel 0 capture/compare free polarity When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2’b00, these bits specifie the multi mode channel 0 output signal polarity.
Page 880 GD32G553 User Manual counter value at the last capture event. And this bit-field is read-only. When multi mode channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 881 GD32G553 User Manual Bits Fields Descriptions 31:29 Reserved Must be kept at reset value. BRK0CMP3P BREAK0 CMP3 input polarity This bit is used to configure the CMP3 input polarity, and the specific polarity is determined by this bit and the BRK0P bit.
Page 882 GD32G553 User Manual determined by this bit and the BRK0P bit. 0: BRKIN0 input signal will not be inverted (BRK0P =0, the input signal is active low; BRK0P =1, the input signal is active high) 1: BRKIN0 input signal will be inverted (BRK0P=0, the input signal is active high;...
Page 883 GD32G553 User Manual This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. BRK0HPDFEN BREAK0 HPDF input 0: HPDF input disabled 1: HPDF input enabled Note: HPDF inputs are different for TIMER15 (HPDF_BREAK[1]) and TIMER16 (HPDF_BREAK[2]).
Page 884 GD32G553 User Manual OCPRE_CLR inputs selection TIMER15 / 16 OCPRE_CLR0 CMP0_OUT OCPRE_CLR1 CMP1_OUT OCPRE_CLR2 CMP2_OUT OCPRE_CLR3 CMP3_OUT OCPRE_CLR4 CMP4_OUT OCPRE_CLR5 CMP5_OUT OCPRE_CLR6 CMP6_OUT OCPRE_CLR7 CMP7_OUT This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP0 register is 00. 18:0...
Page 885 GD32G553 User Manual DTMODE Reserved DTDIFEN Reserved DTFCFG[7:0] Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. DTMODEN Dead time modified on-the-fly enable 0: Dead time value modified on-the-fly disable 1: Dead time value modified on-the-fly enable This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP0 register is 00.
Page 886 GD32G553 User Manual Reserved DMATC[5:0] Reserved DMATA[5:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 DMATC[5:0] DMA transfer count This field defines the times of accessing(R/W) the TIMERx_DMATB register by DMA. 6’b000000: transfer 1 time 6’b000001: transfer 2 times …...
Page 887 GD32G553 User Manual be accessed. The transfer count is calculated by hardware, and ranges from 0 to DMATC. Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CCUSEL CREPSEL CHVSEL OUTSEL...
Page 888: Figure 23-143. Basic Timer Block Diagram
GD32G553 User Manual 23.5. Basic timer (TIMERx, x=5, 6) Overview 23.5.1. The basic timer module(TIMER5 / 6) has a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate a DMA request and a TRGO0 to connect to DAC.
Page 889: Figure 23-144. Normal Mode, Internal Clock Divided By 1
GD32G553 User Manual Figure 23-144. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor ranging from 1 to 65536.
Page 890: Figure 23-146. Timing Chart Of Up Counting Mode, Psc=0/1
GD32G553 User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. The update event is generated each time when counter overflows.
Page 891: Figure 23-147. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32G553 User Manual Figure 23-147. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR value ARSE = 1 CNT_REG 114 115 116 117 118 119 120...
Page 892: Figure 23-149. Adjustment Mode Schematic Diagram
GD32G553 User Manual field are automatically updated. To clear the ADMEN bit, must follow the following steps: 1. CEN bit and ARSE bits must be cleared; 2. CARL[19:16] bit-field must be cleared; 3. ADMEN bit must be cleared; 4. Set the CEN bit to 1.
Page 893 GD32G553 User Manual Period CARL[19:16] 1010 1011 1100 1101 1110 1111 UPIF bit backup The UPIF bit backup function is enabled by setting UPIFBUEN in the TIMERx_CTL0 register. The UPIF and UPIFBU bits are fully synchronized and without latency. By using this function, the UPIF bit in the TIMERx_INTF register will be backuped to the UPIFBU bit in the TIMERx_CNT register.
Page 894 GD32G553 User Manual Registers definition (TIMERx, x=5,6) 23.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved UPIFBUE...
Page 895 GD32G553 User Manual DMA request: – The UPG bit is set – The counter generates an overflow event – The slave mode controller generates an update event. 1: When enabled, only counter overflow generates an update interrupt or a DMA request.
Page 896 GD32G553 User Manual generated by the slave mode controller, a TRGO0 pulse occurs. And in the latter case, the signal on TRGO0 is delayed compared to the actual reset. 001: Enable. This mode is used to start several timers at the same time or control a slave timer to be enabled in a period.
Page 897 GD32G553 User Manual Reserved Reserved UPIF rc_w0 Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. UPIF Update interrupt flag This bit is set by hardware when an update event occurs and cleared by software. 0: No update interrupt occurred...
Page 898 GD32G553 User Manual CNT[15:0] Bits Fields Descriptions UPIFBU UPIF bit backup This bit is a backup of UPIF bit in TIMERx_INTF register and read-only. This bit is only valid when UPIFBUEN = 1. If the UPIFBUEN =0, this bit is reserved and read the result is 0.
Page 899 GD32G553 User Manual CARL[19:16] Reserved CARL[15:0] Bits Fields Descriptions 31:28 CARL[19:16] Counter auto reload value (bit 16 to 19) When the PWMADMEN =0, CARL[19:16] bit-field is 0000. When the PWMADMEN =1, CARL[19:16] bit-field specifies fractional part of the auto reload value.
Page 900 GD32G553 User Manual Low power timer (LPTIMER) 24.1. Overview The LPTIMER is a 16-bit timer and it is able to keep running in all power modes except for standby mode with its diversity of clock sources. The LPTIMER provides a flexible mechanism of the clock, which reduces the power consumption to a minimum while also achieving the required functions and performance.
Page 901: Figure 24-1. Lptimer Block Diagram
GD32G553 User Manual 24.3. Block diagram provides details of the internal configuration of the Figure 24-1. LPTIMER block diagram low power timer. Figure 24-1. LPTIMER block diagram High level counter IN1FP IN1F LPTIMER_IN1 Polarity Filter DECODER selection IN0FP Counter IN0F...
Page 902: Figure 24-2. Lptimer Clock Source Selection
GD32G553 User Manual Figure 24-2. LPTIMER clock source selection CKSSEL CK_LPTIMER LPTIMER_CK PSC_CLK LPTIMER_IN0 IN0P Polarity COUNTER selection IN0FP IN0F Polarity Filter selection CKSSEL CNTMEN LPTIMER has the capability of being clocked by either the internal clock signal or external clock signal controlled by bits CNTMEN and CKSSEL in LPTIMER_CTL0 register.
Page 903: Figure 24-3. Internal Clock Mode1 (Ckssel = 0 And Cntmen = 1 And Psc[2:0] = 000)
GD32G553 User Manual For this case, the LPTIMER counter can be clocked either on rising or falling edges of the external input clock signal, but not on both edges. Since the external signal added to the LPTIMER_IN0 pin is also used to clock the LPTIMER core logic, there is some initial delay (after the LPTIMER is enabled) before the counter is counting.
Page 904: Figure 24-4. Input Filter Timing Diagram (Eckflt=2'B01)
GD32G553 User Manual Prescaler divider PSC[2:0] bit-filed 1/128 Input filter 24.4.4. The external (mapped to GPIOs) or internal (mapped on-chip peripherals, such as comparators) signals on the LPTIMER_INx needs to be filtered by a digital filter to prevent the glitches and noise interference from spreading in LPTIMER. This can be used to prevent false counts and triggers.
Page 905: Figure 24-5. External Inputs High Level Counter
GD32G553 User Manual the counter is cleared to 0. The INHLCOIF flag (in LPTIMER_INTF register) is set by hardware when the value of LPTIMER_INx high level counter equal to the value of INHLCMVAL bits (in LPTIMER_INHLCMV register). An interrupr will generated if the INHLCOIE bit is enabled (in LPTIMER_INTEN register).
Page 906: Table 24-2. External Trigger Mapping
GD32G553 User Manual LPTEN bit equals “0”, any write on these bits will be discarded by hardware. External trigger mapping 24.4.7. The LPTIMER external trigger mapping is shown in Table 24-2. External trigger mapping. Table 24-2. External trigger mapping ETSEL[3:0]...
Page 907: Figure 24-6. Lptimer Output With Smst = 1(16-Bit)
GD32G553 User Manual Figure 24-6. LPTIMER output with SMST = 1(16-bit) When the OMSEL bit in the LPTIMER_CTL0 register is set, the set mode is enable. In this case, the counter is only started once after the first trigger, and all subsequent trigger events is ignored, as shown in Figure 24-7.
Page 908: Figure 24-8. Lptimer Output With Ctnmst = 1(16-Bit)
GD32G553 User Manual Figure 24-8. LPTIMER output with CTNMST = 1(16-bit) ignored ignored External Trigger CARL[15:0] CMPVAL[15:0] COUNT LPTIMER_O The SMST and CTNMST bits can be only when the timer is enabled (the LPTEN bit modified is set). And the single counting mode and continuous counting mode can be modified on the fly.
Page 909: Output Mode
GD32G553 User Manual Output Mode 24.4.10. By configuring the LPTIMER_CARL register and LPTIMER_CMPV register, the LPTIMER can output several different waveforms. The LPTIMER can generate the following waveforms:  PWM mode: the LPTIMER output is set when a match occurs between the value of LPTIMER_CMPV and the LPTIMER_CNT registers.
Page 910: Figure 24-9. Lptimer_O Output Mode With Opsel Bit(16-Bit)
GD32G553 User Manual Figure 24-9. LPTIMER_O output mode with OPSEL bit(16-bit) CARL[15:0] CMPVAL[15:0] COUNT OPSEL = 0 Single pulse mode Set mode OPSEL = 1 Single pulse mode Set mode Timeout mode 24.4.11. By setting the TIMEOUT bit, a valid edge detected on a selected trigger input can be used to reset the LPTIMER counter.
Page 911: Figure 24-10. Lptimer Timeout Mode(16-Bit)
GD32G553 User Manual Figure 24-10. LPTIMER timeout mode(16-bit) External Trigger TIMEOUT = 0 ignored CARL[15:0] CMPVAL[15:0] COUNT TIMEOUT = 1 CARL[15:0] CMPVAL[15:0] Counter CMPVMIE = 1 CMPVMIF Clear flag LPTIMER_ WAKEUP Decoder mode 24.4.12. The LPTIMER has two decoder modes: ...
Page 912: Figure 24-11. Counter Operation In Decoder Mode 0 With Rising-Edge-Mode
GD32G553 User Manual Therefore, users must configure the LPTIMER_CAR register before the counter starts to count. When the counter direction changes, the corresponding flag is set. When the counter direction moves from up to down, the DOWNIF bit is set. When the counter direction moves from down to up, the UPIF bit is set.
Page 913: Figure 24-12. Counter Operation In Decoder Mode 0 With Falling-Edge-Mode
GD32G553 User Manual Figure 24-12. Counter operation in decoder mode 0 with falling-edge-mode IN0F IN1F CARL Counter Down Down UPIF DOWNIF Decoder mode 1 The decoder mode 1 function uses two non-quadrature inputs derived from the LPTIMER_IN0 and LPTIMER_IN1 pins respectively to generate the counter value.
Page 914: Figure 24-13. Counter Operation In Decoder Mode 1 With Non-Inverted
GD32G553 User Manual Figure 24-13. Counter operation in decoder mode 1 with non-inverted IN1FP IN0FP CARL Counter IN1FP IN0FP CARL Counter When the inputs of LPTIMER_IN0 and LPTIMER_IN1 do not meet the timing relationship in non-inverted, the counter Figure 24-13. Counter operation in decoder mode 1 with cannot count.
Page 915: Figure 24-15. Counter Operation In Decoder Mode 1 With Non-Inverted(In0Eif)
GD32G553 User Manual Figure 24-15. Counter operation in decoder mode 1 with non-inverted(IN0EIF) IN1FP IN0FP CARL Counter IN0EIF Figure 24-16. Counter operation in decoder mode 1 with non-inverted(INRFOEIF) IN1FP IN1FP IN0FP IN0FP CARL CARL Counter Counter INRFOEIF INRFOEIF Figure 24-17. Counter operation in decoder mode 1 with non-inverted(INHLOEIF)
Page 916: Table 24-4. Lptimer Works In Low-Power Modes
GD32G553 User Manual provided ( 0) and the internal clock of LPTIMER cannot be prescaled (PSC [2:0] = CKSSEL = 000). In this case, the internal clock signal frequency should be at least four times the frequency of the external clock signal.
Page 917: Table 24-5. Lptimer Interrupt Events
GD32G553 User Manual Interrupts 24.4.15. The following events can generate interrupts or wake-up events, if they are enabled through the LPTIMER_INTEN register:  LPTIMER_IN1 error LPTIMER_IN0 error  The falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error ...
Page 918 GD32G553 User Manual Interrupt event Description change down to up to up. Counter auto reload register Interrupt flag is set when the APB bus write operation to the update LPTIMER_CAR register has been successfully completed. Interrupt flag is set when the APB bus write operation to the Compare value register update LPTIMER_CMPV register has been successfully completed.
Page 919 GD32G553 User Manual 24.5. Register definition LPTIMER base address: 0x4000 9400 Interrupt flag register (LPTIMER_INTF) 24.5.1. Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word (32-bit). HLCMV IN1EIF IN0EIF INRFOEIF INHLOEIF INHLCOIF Reserved UPIF ETED...
Page 920 GD32G553 User Manual Note: This flag just used in decoder mode 1. INHLCOIF LPTIMER_INx(x=0,1) high level counter overflow interrupt flag This flag is set by hardware when LPTIMER_INx high level counter equal to external input high level counter max value register (LPTIMER_INHLCMV). INHLCOIF flag can be cleared by writing 1 to the INHLCOIC bit in the INTC register.
Page 921 GD32G553 User Manual CMPVMIC bit in the INTC register. Interrupt flag clear register (LPTIMER_INTC) 24.5.2. Address offset: 0x04 Reset value: 0x0000 This register has to be accessed by word (32-bit). HLCMV IN1EIC IN0EIC INRFOEIC INHLOEIC INHLCOIC Reserved UPIC ETED CMPV...
Page 922 GD32G553 User Manual CMPVUPIC Compare value register update interrupt flag clear bit. Write 1 to this bit to clear the CMPVUPIF flag, and write 0 has no effect. ETEDEVIC External trigger edge event interrupt flag clear bit. Write 1 to this bit to clear the ETEDEVIF flag, and write 0 has no effect.
Page 923 GD32G553 User Manual INHLOEIE The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit. 0: Disabled 1: Enabled This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). INHLCOIE...
Page 924 GD32G553 User Manual This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). CARMIE Counter auto reload register match interrupt enable bit 0: Disabled 1: Enabled This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0).
Page 925 GD32G553 User Manual LPTIMER_CTL1 register is 0). CNTMEN Counter mode select This bit is used to select the clock source of the LPTIMER counter. 0: The counter is count with each internal clock pulse 1: The counter is count with each active clock pulse on the LPTIMER_IN0.
Page 926 GD32G553 User Manual 01: Falling edge of external trigger enable 11: Rising and falling edges of external trigger enable These bits can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). Reserved Must be kept at reset value.
Page 927 GD32G553 User Manual source must be used in this function. 00: Filter disabled, any active level of the trigger is valid. 01: The active level change of the trigger need to be maintained at least 2 clock periods. 10: The active level change of the trigger need to be maintained at least 4 clock periods.
Page 928 GD32G553 User Manual edges, the LPTIMER must be clocked by an internal clock source, and the internal clock frequency is at least equal to four times the external clock frequency. If the LPTIMER is configured in decoder mode 0, the decoder both-edge-mode is active.
Page 929 GD32G553 User Manual RDRSTEN Read cause LPTIMER_CNT asynchronously reset enable This bit is set and reset by software. 0: Read cause LPTIMER_CNT register asynchronously reset disabled 1: Read cause LPTIMER_CNT register asynchronously reset enabled This bit can be modified only when the LPTIMER is enabled (The LPTEN bit in LPTIMER_CTL1 register is 1).
Page 930 GD32G553 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMPVAL[15:0] Compare value This bit-filed specifies the compare value of the counter. This bit-filed can be modified only when the LPTIMER is enabled (The LPTEN bit in LPTIMER_CTL1 register is 1).
Page 931 GD32G553 User Manual 15:0 CNT[15:0] Counter value Note: When the LPTIMER uses an asynchronous clock, reads the LPTIMER_CNT register may return unreliable values. So it is necessary to perform two consecutive read operations and confirm whether the two read values are the same.
Page 932 GD32G553 User Manual Input high level counter max value register (LPTIMER_INHLCMV) 24.5.10. Address offset: 0X24 Reset value: 0x0000 This register has to be accessed by word (32-bit). INHLCMVAL [25:16] Reserved INHLCMVAL [15:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value.
Page 933: Block Diagram
GD32G553 User Manual High-Resolution Timer (HRTIMER) Overview 25.1. HRTIMER has a high-resolution counting clock and can be used for high-precision timing. It can generate 16 high resolution and flexible digital signals to control motor or be used for power management applications. The 16 digital signals can be output independently or coupled into 8 pairs of complementary signals.
Page 934: Figure 25-1. Hrtimer Block Diagram
GD32G553 User Manual Figure 25-1. HRTIMER block diagram Master_TIMER repetition counter auto Synchronization DMA mode register DMA request DMA request reload register control output/input ADC trigger DAC trigger Counter Compare Slave_TIMERx (x= 0..7) repetition counter auto register reload register STxCH0_O...
Page 935: Figure 25-2. Master_Timer Diagram
GD32G553 User Manual Figure 25-2. Master_TIMER diagram Slave_TIMERx(x=0..7) CREP Counter repetition Synchronization Start counter input Reset Counter HRTIMER_PSCCK HRTIMER_HPCK CMP0 32 * f HRTIMER_CK HRTIMER_CK Half mode CMP1 (from RCU) Alternate mode HRTIMER_CK CMP2 CMP3 The auto-reload register and compare y (y=0..3) register have the following limitations: ...
Page 936: Figure 25-3. Counter Clock When Divided By 32
GD32G553 User Manual CNTCKDIV[2:0] HRTIMER_PSCCK HRTIMER_HPCK Note: The clock division CNTCKDIV[2:0] cannot be modified once the Master_TIMER is enabled. CNTCKDIV[2:0] is in HRTIMER_MTCTL0 register. shows some behavior of the counter when Figure 25-3. Counter clock when divided by 32 the register HRTIMER_MTCAR is set to 0x104 as well as the field CNTCKDIV[2:0] is set to 3’b100.
Page 937: Figure 25-4. Counter Behavior In Single Pulse Mode
GD32G553 User Manual Figure 25-4. Counter behavior in single pulse mode MTCEN or STxCEN(x=0..7) Reset event CARL CARL CARL Counter when CTNM = 0 CNTRSTM = 0 CARL CARL Counter when CTNM = 0 CNTRSTM = 1 In continuous mode, the counter starts immediately as soon as MTCEN bit in HRTIMER_MTCTL0 register is set to 1.
Page 938: Figure 25-6. Repetition Counter Behavior In Continuous Mode
GD32G553 User Manual to REPIFC bit in HRTIMER_MTINTFC. shows repetition counter Figure 25-6. Repetition counter behavior in continuous mode operation diagram in continuous mode. Figure 25-6. Repetition counter behavior in continuous mode MTCEN or STxCEN(x=0..7) Reset event CARL[15:0] Counter when CTNM = 1...
Page 939: Counter Reset
GD32G553 User Manual Figure 25-8. Repetition counter behavior in single pulse mode with CNTRSTM = 1 MTCEN or STxCEN(x=0..7) Reset event CARL CARL Counter when CTNM = 0 CNTRSTM = 1 CREP[7:0] 0x03 Repetition 0x03 0x02 0x01 0x00 0x03 counter...
Page 940: Table 25-3. Alternate Mode Selection
GD32G553 User Manual enabled (CMPxIE = 1 or CMPxDEN = 1 bits in HRTIMER_MTDMAINTEN register where x=0..3). The compare interrupt flag can be cleared by writing 1 to CMPxIFC bit in HRTIMER_MTINTFC where x=0..3. Half mode When HALFM bit in HRTIMER_MTCTL0 is set 1, the half mode is enabled. This mode forces the value of compare 0 active register to be half of the counter-reload value, but the value of HRTIMER_MTCMP0V register is not updated with the HRTIMER_MTCAR / 2 value.
Page 941: Table 25-5. Master_Timer Shadow Registers And Update Event
GD32G553 User Manual HRTIMER_MTCTL0 register and start counter when SYNISTRT is set to 1 in HRTIMER_MTCTL0 register. Refer to for more information. Synchronization input A synchronization input request will set the SYNIIF bit in HRTIMER_MTINTF register to 1, and a interrupt or a DMA request is issued if enabled(SYNIIE = 1 or SYNIDEN = 1 bits in HRTIMER_MTDMAINTEN register).The synchronization input interrupt flag can be cleared...
Page 942 GD32G553 User Manual UPSEL[1:0]=2’b01 in HRTIMER_MTCTL0 register, An update event is automatically generated by the hardware when the DMA transfer is completed in DMA mode. It is also possible to generate update event by software or repetition event. Update event generated on counter roll-over following a DMA transfer completion in DMA mode.
Page 943: Figure 25-10. Slave_Timerx Diagram
GD32G553 User Manual Figure 25-10. Slave_TIMERx diagram Master_TIMER repetition CREP counter Synchronization Capture 0 Start input Reset Capture 1 Counter HRTIMER_CK (from RCU) HRTIMER_PSCCK HRTIMER_CK HRTIMER_HPCK 32 * f HRTIMER_CK CMP0 Delayed EXEVy mode CMP1 Half mode External event x filter: EXEVyC(y=0..9)
Page 944: Repetition Counter
GD32G553 User Manual 3’b111 Note: “x” means that all bits are significant. Counter clock The clock source of Slave_TIMERx is the HRTIMER_CK from module RCU. The DLL is used to produce a high resolution clock HRTIMER_HPCK (f = 32 * f ).
Page 945 GD32G553 User Manual the repetition counter has reached zero, the coming roll-over event in continuous mode or reset event will generate a repetition event and reload the value of HRTIMER_STxCREP register. The repetition event will set REPIF bit in HRTIMER_STxINTF register to 1, and a repetition interrupt or DMA request is issued if enabled (REPIE = 1 or REPDEN = 1 bits in HRTIMER_STxDMAINTEN register).The repetition interrupt flag can be cleared by writing 1...
Page 946 GD32G553 User Manual  External event y(y=0..9): EXEVy conditioned by external event filter in Slave_TIMERx. When the counter clock HRTIMER_PSCCK prescaling ratio is above 16 (CNTCKDIV[2:0] > 3’b101), the counter reset event is delayed to the next rising edge of the HRTIMER_PSCCK.
Page 947: Figure 25-11. Capture 0 Triggered By Exev0 And Exev1
GD32G553 User Manual Figure 25-11. Capture 0 triggered by EXEV0 and EXEV1 Capture 0 event Capture 0 event Capture 0 event HRTIMER_CK HRTIMER_PSCCK 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x00 0x01 0x02 Counter Capture signal: EXEV0 Capture signal:...
Page 948: Table 25-7. Alternate Mode Selection
GD32G553 User Manual the compare 0 active register is refreshed on the update event. Otherwise, the compare 0 active register is refreshed as soon as the new value is written. Alternate mode This mode helps achieve an alternate topology that complements the half mode. The compare value registers are automatically recalculated when the HRTIMER_STxCREP value is updated.
Page 949: Figure 25-13. Compare Delayed Mode Chart
GD32G553 User Manual In the above application condition, re-write the comparison value HRTIMER_STxCMP0V and HRTIMER_STxCMP2V, and the difference value between them is greater than 3, then the normal output is restored. Exchange mode The two outputs CH0 and CH1 of slave timer can be exchange bysetting EXCx in HRTIMER_CTL1.and the output of two channels is effective when next update event occur.
Page 950: Figure 25-14. Compare 1 Delayed Mode 0
GD32G553 User Manual associated with capture 1 and compare 0/2. Note: The recalculated value is transferred to an internal register which cannot read. The DELCMP3M[1:0] (compare 3) and DELCMP1M[1:0] (compare 1) in HRTIMER_STxCTL0 register can be used to configure the delay mode. Take DELCMP1M[1:0] for example：...
Page 951: Figure 25-15. Compare 1 Delayed Mode 1
GD32G553 User Manual Compare 1 delayed mode Figure 25-15. Compare 1 delayed mode 1 Capture 0 event Compare 0 event Update event Capture 0 event Compare 1 event Compare 1 event HRTIMER_CK HRTIMER_PSCCK 0x00 0x01 0x02 0x03 0x04 0x05 0x06...
Page 952: Figure 25-16. Compare Delayed Mode With Shwen = 0
GD32G553 User Manual Figure 25-16. Compare delayed mode with SHWEN = 0 MTCEN or STxCEN(x=0..4) previous+ C1 C2+ C1 update event Counter when CTNM = 1 Preload=previous Active=previous + C1 Capture event C a p t u r e C a p t u r e...
Page 953: Figure 25-17. Variable Frequency Half Mode
GD32G553 User Manual Figure 25-17. Variable frequency half mode EXEV0 EXEV0 EXEV0 EXEV0 HRTIMER_STxCMP1V HRTIMER_STxCMP0V EXEV1 EXEV1 EXEV1 EXEV1 HRTIMER_STxCH0 EXEV2 EXEV2 EXEV2 EXEV2 HRTIMER_STyCH0 Blanking HRTIMER_STxCH1 As shown in Figure 25-17. Variable frequency half mode.  HRTIMER_STxCH0 is SET by external event 0 (EXEV0), and RESET by external event 1 (EXEV1), EXEV0 trigger the capture event of master vonverter(Slave_TIMERx).
Page 954: Figure 25-18. Pwm Waveform When Impud = 1 And Imupd = 0
GD32G553 User Manual Figure 25-18. PWM waveform when IMPUD = 1 and IMUPD = 0 Counter CMP2 IMUPD =1 Set on period reset on CMP2 IMUPD =0 Set on period reset on CMP2 Set/reset crossbar The channel output waveform can be divided into three stages: ...
Page 955: Figure 25-20. O0Pre Wave: Set On Cmp0, Reset On Cmp1
GD32G553 User Manual When the event configured in HRTIMER_STxCHySET register occurs, this module produces a “set request” and make the OyPRE high. When the event configured in HRTIMER_STxCHyRST occurs, this module produces a “reset request” and make the OyPRE low. If the same event is configured in HRTIMER_STxCHySET and HRTIMER_STxCHyRST registers, this module produces a “toggle request”...
Page 956: Table 25-9. Slave_Timer Interconnection Event
GD32G553 User Manual Table 25-9. Slave_TIMER interconnection event Inter-connection T0 ST0 T0 ST1 T0 ST2 T0 ST3 T0 ST4 T0 ST5 T0 ST6 T0 ST7 CMP0 × × × × × CMP1 × × × × × From ST0 CMP2 ×...
Page 957: Figure 25-21. Oypre Wave In Center-Aligned Mode
GD32G553 User Manual and then counts down to 0 alternatively. The mode is enabled by setting CAM bit in HRTIMER_STxCTL1, Center-aligned counting mode only used in Slave_TIMERx(x = 0..7) not for Master_TIMER. The period of Slave_TIMERx in HRTIMER_STxCAR only can be preloaded when period event or reset event occurs.
Page 958: Figure 25-22. Counter Repetition Value Crep[7:0] And Rovm[1:0] In Center Aligned Mode
GD32G553 User Manual HRTIMER_STxCAPyV register shows the direction of the count. The period event used to set or reset OxPRE is defined in ROVM[1:0] bits in HRTIMER_STxCTL1 register. When ROVM[1:0] = 2b00, the period event is generated when the counter is equal to 0 or to HRTIMER_STxCAR value, when ROVM[1:0] = 2b01 the period event is generated when the counter is equal to 0, when ROVM[1:0] = 2b10 the period event is generated when the counter is equal to HRTIMER_STxCAR.
Page 959 GD32G553 User Manual EXEV0FM[4:0] Up counting mode Center aligned mode compare 2 compare 2, only during the down-counting in center aligned mode Windowing from another timing Windowing from compare 1 unit during the up-counting to 01111 compare 2 during the down-...
Page 960: Figure 25-23. Arbitration Mechanism During Each T
GD32G553 User Manual Figure 25-23. Arbitration mechanism during each t period HRTMER_CK Arbiter0: STx interconnection Arbiter1: only one event Arbiter2: CMP3> event y(y=0..10) delay and request reset> CMP2> smaller, toggle> CMP1> priority CMP0> higher >PER Arbiter0: Master_TIMER events CMP3> only one event and request CMP2>...
Page 961: Figure 25-24． Arbitration Mechanism Example
GD32G553 User Manual  HRTIMER_STxCH0RST = 0x0198 0344 and selected events producing “reset request” are: From Master_TIMER: compare 0 event, compare 1 event. From Slave_TIMER0 itself: compare 3 event, period event. Interconnection event to Slave_TIMER0: interconnection event 7 (Slave_TIMER4 compare 2 event), interconnection event 8 (Slave_TIMER4 compare 3 event).
Page 962: Figure 25-25. A Pulse Of 1 T Hrtmer_Ck
GD32G553 User Manual of 1 t period is generated. Refer to Figure 25-25. A pulse of 1 tHRTMER_CK period. HPTMER_CK Figure 25-25. A pulse of 1 t period HRTMER_CK HRTIMER_CK HRTIMER_CK OxPRE postponed high-resolution HRTIMER_CK OxPRE high-resolution anticipated high-resolution OxPRE...
Page 963: Figure 25-28. Oxpre Wave With Cntckdiv[2:0] = 3'B110
GD32G553 User Manual An “set or reset request” occurring within the HRTIMER_PSCCK cycle is delayed to the next active edge of the HRTIMER_PSCCK, even if the arbitration is still performed every t HRTIMER_CK cycle. When “set and reset requests” from different event sources simultaneously occur in a tHRTIMER_CK cycle, the “reset request”...
Page 964 GD32G553 User Manual O0PRE will be set to high level.  HRTIMER_STxCH0RST = 0x0000 0010: compare 1 event produces “reset request” and O0PRE will be set to low level.  HRTIMER_STxCMP0V = 0x0060  HRTIMER_STxCMP1V = 0x00E0 Figure 25-29. C0OPRE wave in regular mode...
Page 965: Figure 25-30. C0Opre And C1Opre Complementary Wave With Dead-Time
GD32G553 User Manual active to inactive level, CH0ONAIF bit in HRTIMER_STxINTF register will be set to 1, and a output inactive interrupt or a DMA request is issued if enabled (CH0ONAIE = 1 or CH0ONADEN = 1 bit in HRTIMER_STxDMAINTEN register). The CH0ONAIF interrupt flag can be cleared by writing 1 to CH0ONAIFC bit in HRTIMER_STxINTFC.
Page 966: Figure 25-32. Structure Chart In Balanced Mode
GD32G553 User Manual Figure 25-31. Complementary wave with pulse width less than dead-time O0PRE O0PRE DTRCFG[15:0] DTRCFG[15:0] DTRCFG[15:0] Skip dead-time C0OPRE C0OPRE following rising DTRS = 0 DTRS = 0 DTFS = 0 DTFCFG[15:0] DTFCFG[15:0] DTFS = 0 DTFCFG[15:0] Skip dead-time...
Page 967: Figure 25-33. C0Opre And C1Opre Wave In Balanced Mode
GD32G553 User Manual advised make HRTIMER_STxCH0SET HRTIMER_STxCH1SET HRTIMER_STxCH0RST = HRTIMER_STxCH1RST, in order to achieve a balanced operation with identical waveforms. Still, it is possible to have different programming on both outputs for other uses. The bit CBLNF in HRTIMER_STxINTF register which is reset when the balanced mode is disabled, indicates which channel is currently outputting the signal (O0PRE or O1PRE).
Page 968: Table 25-11. Crossbar And Idle Control Stage Work Together
GD32G553 User Manual IDLE control The stage has three ways to control the IDLE state:  Delayed IDLE  Balanced IDLE  IDLE controlled by bunch mode Delayed IDLE and balanced IDLE cannot use at the same time. Balanced IDLE is only available in balanced mode.
Page 969: Figure 25-34. Iso0 = 0 And Chop = 0 In Delayed Idle
GD32G553 User Manual The delayed IDLE mode can be applied to a single output (CHyOPRE) or to both outputs (CH0OPRE CH1OPRE) decided bit-field DLYISCH[2:0] HRTIMER_STxCHOCTL register, as follows:  DLYISCH[2:0] = 3’b000: The delayed IDLE mode is applied to CH0OPRE.
Page 970: Figure 25-35. Iso0 = 1 And Chop = 0 In Delayed Idle
GD32G553 User Manual Figure 25-35. ISO0 = 1 and CHOP = 0 in delayed IDLE HRTIMER_STxCMP1V active value Conuter HRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 1 CH0P = 0 CH0OPRE RUN State IDLE State RUN State re-enable EXEV6...
Page 971: Figure 25-37. Iso0 = 1 And Chop = 1 In Delayed Idle
GD32G553 User Manual Figure 25-37. ISO0 = 1 and CHOP = 1 in delayed IDLE HRTIMER_STxCMP1V active value Conuter HRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 1 CH0P = 1 CH0OPRE RUN State IDLE State RUN State re-enable EXEV6...
Page 972: Figure 25-38. Balanced Idel With Iso0 = 0 And Iso1 = 0
GD32G553 User Manual Figure 25-38. Balanced IDEL with ISO0 = 0 and ISO1 = 0 HRTIMER_STxCMP1V active value Conuter HRTIMER_STxCMP0V active value C0OPRE C1OPRE re-enable DLYIIF set Case 0: BLNIF = previous value BLNIF = 0 EXEV6 CH0OPRE ISO0 = 0...
Page 973: Table 25-13. Output During Idel State Controlled By Bunch Mode
GD32G553 User Manual IDLE controlled by bunch mode In bunch mode, the IDLE state is controlled by bunch controller. Refer to Bunch mode more information. The balanced IDLE and delayed IDLE has a higher priority than the bunch mode: when the balanced IDLE or delayed IDLE has been triggered, the output is kept with IDLE state after exiting from bunch mode.
Page 974: Figure 25-39. Stxchy_O Wave With Chyp=0 Or Chyp=1
GD32G553 User Manual The output polarity is programmed using CHyP bits in HRTIMER_STxCHOCTL register. When CHyP = 0, the polarity is output active high. When CHyP = 1, the polarity is output active low. Refer to Figure 25-39. STxCHy_O wave with CHyP=0 or CHyP=1.
Page 975: Figure 25-40. Carrier-Signal Structure Diagram
GD32G553 User Manual Figure 25-40. Carrier-signal structure diagram Carrier-signal generator 0 CH0CSEN Carrier-signal generator 1 O0PRE CH1CSEN HRTIMER_CSGCK O1PRE prescaler: CH1CSEN/ CH0CSEN HRTIMER_CK IDLE CH0OPRE CH1OPRE In carrier-signal mode, it is possible to define a specific pulse width before the beginning of the carrier-signal.
Page 976: Figure 25-41. Hrtimer Output With Carrier-Signal Mode Enabled
GD32G553 User Manual Figure 25-41. HRTIMER output with carrier-signal mode enabled Compare 1 active value Slave_TIMER0 Slave_TIMER0 OyPRE OyPRE Carrier-signal Carrier-signal Carrier signal Carrier signal duty duty Carrier signal period CHyOPRE CHyOPRE First pulse First pulse Synchronization input start/reset counter Synchronous input can generate a counter reset event when SYNIRST set 1 in HRTIMER_STxCTL0 register.
Page 977: Table 25-16. Stxupiny(Y=0..2) And Chip Internal Signal
GD32G553 User Manual Table 25-15. Slave_TIMERx shadow registers and common registers and update event Registers Shadow registers Update event. that contain shadow registers enable bit HRTIMER_STxDMAINTEN HRTIMER_STxCAR Software(STxSUP bit) HRTIMER_STxCREP Repetition event(UPREP = 1) HRTIMER_STxCMP0V Counter reset event or roll-over...
Page 978: Figure 25-42. Blanking Mode And Windowing Mode
GD32G553 User Manual  Blanking mode: external events that occur within a specified time are ignored.  Windowing mode: external events that occur within a specified time are taken into account. Refer to Figure 25-42. Blanking mode and windowing mode Figure 25-42.
Page 979 GD32G553 User Manual T0 ST0 T0 ST1 T0 ST2 T0 ST3 T0 ST4 T0 ST5 T0 ST6 T0 ST7 SRC2 SRC0 STBLK STBLK STBLK STBLK CMP0 × × × × SRC0 SRC1 SRC1 SRC1 STBLK STBLK STBLK CMP1 × ×...
Page 980: Table 25-18. Filtering Signals Mapping In Windowing Mode
GD32G553 User Manual T0 ST0 T0 ST1 T0 ST2 T0 ST3 T0 ST4 T0 ST5 T0 ST6 T0 ST7 SRC8 SRC8 SRC8 STBLK STBLK STBLK CMP1 × × × × × SRC8 SRC8 SRC8 CMP3 × × × × ×...
Page 981: Figure 25-43. External Event X Counter
GD32G553 User Manual time is completed. External event counter The 10 external events can be filtered by external event X counter module. As shown in Figure 25-43. External event X counter. Figure 25-43. External event X counter External event counter...
Page 982 GD32G553 User Manual EXEVXCNTTHR[5:0] = 2 External event X count External event (0..9) EXEVXCNTTHR[5:0] 0x02 0x00 0x00 0x01 0x01 0x03 0x02 External event (0..9) Fast external events mode The processing time of external events can be adjusted dynamically according to the actual requirements.
Page 983 GD32G553 User Manual When CLBPEREN bit in HRTIMER_DLLCCTL register is cleared to 0, DLL calibrates the high resolution clock HRTIMER_HPCK only once by writing CLBSTRT to 1. Bunch mode 25.4.4. The bunch mode controller allows to have the CHyOPRE (y=0,1) alternatively in IDLE and RUN state by hardware.
Page 984: Figure 25-45. Bunch Mode Timing Chart
GD32G553 User Manual Table 25-19. Chip internal signal in bunch mode BMCLKy(y=0..3) Chip internal signal BMCLK0 TIMER15_CH0_O BMCLK1 TIMER16_CH0_O BMCLK2 TIMER6_TRGO BMCLK3 Reserved The duration IDLE defined with HRTIMER_BMCMPV register, and HRTIMER_BMCAR register defines the bunch mode period which is the sum of the IDLE and RUN duration.Refer to...
Page 985: Figure 25-46. Regular Entry For Bunch Mode
GD32G553 User Manual When the trigger event occurs, there are two ways to enter bunch mode: regular entry and delayed entry. Regular entry When BMCHyDTI(y=0,1) bit in HRTIMER_STxCHOCTL register is 0, the bunch mode entry is regular. The output will enter the bunch mode and take their idle level (as per ISO0 and ISO1 setting) on the first BM-counter counting clock after the selected event occurs.
Page 986: Figure 25-47. Delayed Entry For Bunch Mode
GD32G553 User Manual When the bunch mode entry arrives during the regular dead-time, it is aborted and a new dead-time is re-started corresponding to the inactive period. Refer to Figure 25-47. Delayed entry for bunch mode with the following configuration: ...
Page 987: Figure 25-48. Emulate Bunch Mode Example
GD32G553 User Manual clock(HRTIMER_PSCCK) is stopped and the counter is reset. Use HRTIMER_STxCMP0CP register to emulate bunch mode The HRTIMER_STxCMP0CP register can be used to produce a waveform similar to that controlled by bunch mode. To do this, the following configuration is required: ...
Page 988: Synchronization Input
GD32G553 User Manual The bit-field SYNOSRC[1:0] in HRTIMER_MTCTL0 register can be configured to selecte the source to be sent to the synchronization output. There are four sources available:  2’b00: Master_TIMER start event. There are three situations in which the generated start...
Page 989: Figure 25-49. Extern Event Y(Y=0..4) Processed Diagram
GD32G553 User Manual External event 25.4.6. There are 10 external events that can be simultaneously used on 8 Slave_TIMER. The external event y(y=0..4) are configured using the HRTIMER_EXEVCFG0 register , and the external event y(y=5..9) configured using HRTIMER_EXEVCFG1 HRTIMER_EXEVDFCTL registers.
Page 990: Table 25-20. External Events Mapping
GD32G553 User Manual (EXEVyEG[1:0]=2’b00).  configured Digital filters configuration: with EXEVyFC[3:0] bit-field HRTIMER_EXEVDFCTL register. The digital filters sampling clock f is defined with EXEVFDIV[2:0] bit-field in HRTIMER_EXEVFCK HRTIMER_EXEVDFCTL register. These external events sources EXEVySRCz(y=0..9,z=0..4) can come from comparators, digital input pins, ADC’s analog watchdogs and TIMER_TRGO. Refer to Table 25-20.
Page 991: Figure 25-51. Fault Input Diagram
GD32G553 User Manual The predefined level is configured by bit-field CHyFLTOS[1:0] in HRTIMER_STxCHOCTL register. The protection mechanism can handle three types of fault sources:  Fault channel: fault event from digital input pin or comparator.  System fault: signals coming from inside the MCU, for example the Cortex ®...
Page 992: Table 25-21. Fault Channel Mapping
GD32G553 User Manual Table 25-21. Fault channel mapping Fault channel FLTyINSRC = 00 (chip FLTyINSRC = 01 FLTyINSRC = 10 external pin) (internal signal) (external event) Fault channel 0 PA12 Comparator 1 external event 0 Fault channel 1 PA15 Comparator 3...
Page 993: Figure 25-52. Fault Counter When Fltxrstm Bit Is 1 And Fltxcnt[2:0] = 0X03
GD32G553 User Manual Fault channel FLTxBLKS = 0,reset and compare FLTxBLKS = 1, compare and windows compare windows Blank start Blank stop Blank start Blank stop reset / update Comparator 2 Comparator 3 Comparator 2 Fault channel 4 Slave_TIMER4 Slave_TIMER4...
Page 994: System Fault
GD32G553 User Manual Fault channel Fault counter reset source Fault channel 3 Slave_TIMER3 reset / update Fault channel 4 Slave_TIMER4 reset / update Fault channel 5 Slave_TIMER5 reset / update Fault channel 6 Slave_TIMER6 reset / update Fault channel 7...
Page 995: Figure 25-53. Trigger To Adc Selection Overview
GD32G553 User Manual Figure 25-53. Trigger to ADC selection overview HRTIMER 0..4,8..12,16..20 HRTIMER_ADCTRIG0 HRTIMER_ADCTRIGS0 HRTIMER_ADCTRIGS0A 0..4,8..12,16..20 HRTIMER_ADCTRIG1 HRTIMER_ADCTRIGS1 HRTIMER_ADCTRIGS1A 0..4,8..12,16..20 HRTIMER_ADCTRIG2 TRIGSEL HRTIMER_ADCTRIGS2 HRTIMER_ADCTRIGS2A 0..4,8..12,16..20 HRTIMER_ADCTRIG3 HRTIMER_ADCTRIGS3 HRTIMER_ADCTRIGS3A HRTIMER_ADCTRIG4 HRTIMER_ADCTRIG5 0..5 HRTIMER_ADCTRIG6 HRTIMER_ADCTRIG7 HRTIMER_ADCTRIG8 HRTIMER_ADCEXTTRG HRTIMER_ADCEXTTRGA HRTIMER_ADCTRIG9 There events which...
Page 996: Figure 25-54. Adc Trigger Division In Up Counting Mode
GD32G553 User Manual Trigger frequency division and other functions are set in HRTIMER_ADCTRIGS0- HRTIMER_ADCTRIGS9 in order to be more compatible with ADC triggering. It should be noted that these trigger sources are connected to TRIGSEL, and TRIGSEL decides what module to trigger.
Page 997: Figure 25-55. Adc Trigger Division In Center Aligned Mode
GD32G553 User Manual Figure 25-55. ADC trigger division in center aligned mode Conuter ADCxPSC[4:0] = 0 ROVM[1:0] =00 ADCxPSC[4:0] = 1 ROVM[1:0] = 01 ADCxPSC[4:0] =1 ROVM[1:0] = 10 ADCxPSC[4:0] = 3 ROVM[1:0] =00 ADCxPSC[4:0] = 4 ROVM[1:0] =01 Trigger to DAC 25.4.9.
Page 998: Figure 25-56. Trigger To Dac Selection Overview
GD32G553 User Manual Figure 25-56. Trigger to DAC selection overview Master_TIMER No trigger Update event HRTIMER_DACTRIG0 DACTRGS[1:0] in HRTIMER_MTCTL0 HRTIMER_DACTRIG1 Slave_TIMERx No trigger HRTIMER_DACTRIG2 Update event DACTRGS[1:0] in HRTIMER_STxCTL0 An output pulse of 32 f clock periods is generated on the DAC triggers output. The synchronization pulse is followed by an idle level of 32 APB clock cycles during which any new DAC update request is ignored.
Page 999: Figure 25-57. Trigger To Dac When Trig0M = 0 And Trig1M = 0
GD32G553 User Manual this mode, the DAC outputs a sawtooth signal that gradually decreases, with the period of the sawtooth wave synchronized with the period of the PWM wave. The DAC module can customize which signal to trigger the DAC to produce a step or reset signal based on the trigger signal from TRIGSEL.
Page 1000: Figure 25-58. Trigger To Dac When Trig0M = 1 And Trig1M = 1
GD32G553 User Manual Figure 25-58. Trigger to DAC when TRIG0M = 1 and TRIG1M = 1 CMP0 HRTIMER_STx_TRIG1 HRTIMER_STx_TRIG0 Output 0 DAC output TRIG1M =1, the trigger is generated on output 0 set event TRIG0M = 1,the trigger is generated on output 0 reset event Interrupt 25.4.11.