GigaDevice Semiconductor GD32H73 Series Errata Sheet
  1. Manuals
  2. Brands
  3. GigaDevice Semiconductor Manuals
  4. Microcontrollers
  5. GD32H73 Series
  6. Errata sheet

GigaDevice Semiconductor GD32H73 Series Errata Sheet

Device limitations
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
GigaDevice Semiconductor Inc.
Device Limitations of GD32H73x/H75x
Errata Sheet

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the GD32H73 Series and is the answer not in the manual?

Questions and answers

Related Manuals for GigaDevice Semiconductor GD32H73 Series

Summary of Contents for GigaDevice Semiconductor GD32H73 Series

  • Page 1 GigaDevice Semiconductor Inc. Device Limitations of GD32H73x/H75x Errata Sheet...

  • Page 2: Table Of Contents

    Device Limitations of GD32H73x/H75x Table of Contents Table of Contents ......................2 List of Figures ........................ 4 List of Tables ........................5 Introduction ......................6 1.1. Revision identification ....................6 1.2. Summary of device limitations ................... 6 Descriptions of device limitations ............... 9 2.1.
  • Page 3 Device Limitations of GD32H73x/H75x 2.9.4. In mute mode, the parity error caused by non-wake frames will set PERR bit ..... 14 2.10. OSPI ........................14 2.10.1. Interrupt and DMA functions are invalid when OSPI is used in indirect write mode ....14 2.10.2.

  • Page 4: List Of Figures

    Device Limitations of GD32H73x/H75x List of Figures Figure 1-1. Device revision code of GD32H73x/H75x ................ 6...

  • Page 5: List Of Tables

    Device Limitations of GD32H73x/H75x List of Tables Table 1-1. Applicable products ......................6 Table 1-2. Device limitations ........................ 6 Table 3-1. Revision history ......................... 18...

  • Page 6: Introduction

    Device Limitations of GD32H73x/H75x Introduction This document applies to GD32H73x/H75x product series, as shown in Table 1-1. Applicable products. It offers technical guidance for using GD32MCU and provides workaround to current device limitations. Table 1-1. Applicable products Type Part Numbers GD32H737xx series GD32H757xx series GD32H759xx series...
  • Page 7 Device Limitations of GD32H73x/H75x Workaround Module Limitations Rev. Rev. Code A Code C Chip damage risk in SMPS mode of the LQFP package VDDSMPS cannot be connected to a low level when not using SMPS GPIO PXY pin connects to PXY_C pin in standby mode TRNG LFSR algorithm failure SWD and JTAG debug function failure when using low...
  • Page 8 Device Limitations of GD32H73x/H75x Workaround Module Limitations Rev. Rev. Code A Code C USBHS USBHS OTG sensitivity problem Note: Y = Limitation present, workaround available N = Limitation present, no workaround available '--' = Limitation fixed...

  • Page 9: Descriptions Of Device Limitations

    Device Limitations of GD32H73x/H75x Descriptions of device limitations SYSTEM 2.1. SysTick is clocked with the system clock (CK_SYS) divided by 2 when 2.1.1. using external clock source Description & impact When SysTick uses external clock source, the SysTick clock is CK_SYS / 2 instead of CK_SYS / 8.

  • Page 10: Pmu

    Device Limitations of GD32H73x/H75x 3. Unlock the FMC_CTL register if necessary. Otherwise, the protection-removed mass erase function cannot be disabled. Information regarding the protection-removed mass erase can be found in Chapter 3.3.5 of the user manual. Workarounds Not available. 2.3. Chip damage risk in SMPS mode of the LQFP package 2.3.1.

  • Page 11: Trng

    Device Limitations of GD32H73x/H75x TRNG 2.5. LFSR algorithm failure 2.5.1. Description & impact The LFSR (Linear Feedback Shift Register) algorithm for generating random numbers is not functioning. Workarounds Do not use LFSR; instead, use the NIST (National Institute of Standards and Technology) algorithm.

  • Page 12: Adc

    Device Limitations of GD32H73x/H75x 2.7. The analog watchdog threshold comparison fails when used 2.7.1. simultaneously with oversampling in a 14-bit ADC Description & impact When the oversample function is enabled in a 14-bit ADC (ADC0/ADC1), the analog watchdog function fails because it does not compare the accumulated sum with the low threshold.

  • Page 13: Usart

    Device Limitations of GD32H73x/H75x USART 2.9. When USART FIFO is enabled, the last byte of the frame cannot be 2.9.1. transmitted Description & impact When USART FIFO function is enabled, USART will not transmit the last byte of a frame. For example, when transmitting ten characters '0123456789', the character '9' will not be transmitted.

  • Page 14: In Mute Mode, The Parity Error Caused By Non-Wake Frames Will Set Perr Bit

    Device Limitations of GD32H73x/H75x set. In mute mode, the parity error caused by non-wake frames will set PERR 2.9.4. Description & impact In mute mode, a parity error caused by a non-wake frame will result in a parity error (the PERR bit in the USART_STAT register is set) when no parity error is found in the wake frame.

  • Page 15: Exmc

    Device Limitations of GD32H73x/H75x subsequent operations, which results in an exception. Workarounds Add a hardware delay (such as 20ms delay) before each poll of memory state. EXMC 2.11. NAND/NOR cannot be used with SDRAM at the same time 2.11.1. Description & impact NAND/NOR cannot be used with SDRAM due to an address conflict during SDRAM refresh.

  • Page 16: Lpdts

    Device Limitations of GD32H73x/H75x LPDTS 2.12. The temperature sensor ready flag cannot be cleared after disabling 2.12.1. LPDTS Description & impact The temperature sensor ready flag (TSRF) cannot be cleared after disabling LPDTS (Low power digital temperature sensor). Workarounds Reset the LPDTS peripheral before enabling LPDTS. 2.13.

  • Page 17: The Can Peripheral Cannot Function Without Using Hxtal

    Device Limitations of GD32H73x/H75x The CAN peripheral cannot function without using HXTAL 2.13.3. Description & impact The CAN peripheral cannot work when the HXTAL clock is not enabled. Workarounds Turn on the HXTAL clock and wait for HXTAL clock stabilization before configuring the CAN peripheral clock source, then you can shut down the HXTAL clock as needed.

  • Page 18: Revision History

    Device Limitations of GD32H73x/H75x Revision history Table 3-1. Revision history Revision No. Description Date Initial Release Sep.12 2023 Update descriptions of contents Sep.26 2023 1. Add limitations of Rev. Code C 2. Add USART / OSPI / EXMC peripherals Apr.20 2024 limitations...
  • Page 19 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

This manual is also suitable for:

Gd32h75 seriesGd32h737 seriesGd32h757 seriesGd32h759 series

Table of Contents