Crystal - Espressif Systems ESP32-C6 Series Hardware Design Manuallines

3 PCB Layout Design
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.
• If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to
employ a square grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in
Figure 17. This can avoid tin leakage when soldering the module EPAD to the substrate.
Figure 18: ESP32-C6 Analog Power Traces in a Four-layer PCB Design

3.4 Crystal

Figure 19 is the crystal layout for reference. Please only maintain a keep-out area around the crystal on the top
layer, and:
• The crystal should be placed far from the clock pin to avoid the interference on the chip. The gap should
be at least 2.4 mm. It is good practice to add high-density ground vias stitching around the clock trace for
better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
• Components in series to the crystal trace should be placed close to the chip side.
• The external matching capacitors should be placed on the two sides of the crystal, not connected directly
to the series components, and at the end of the clock trace, to make sure the ground pad of the capacitor
is close to that of the crystal.
• Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace
under the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as
far away from the clock trace as possible, and the two sides of the clock trace should be surrounded by
grounding copper.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause
interference, for example large inductance component, and ensure that there is a clean large-area ground
plane around the crystal.
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ESP32-C6 Series Hardware Design Guidelines v1.0