Espressif Systems ESP32-C6 Series Hardware Design Manuallines page 24

3 PCB Layout Design
3.5 RF
The RF trace is routed as shown highlighted in pink in Figure 20.
Figure 20: ESP32-C6 RF Layout in a Four-layer PCB Design
• The RF trace should have 50 Ω characteristic impedance. The reference plane is the second layer. A
π-type matching circuit should be added on the RF trace and placed close to the chip, in a zigzag.
• For designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown in Figure
21.
Espressif Systems
Figure 19: ESP32-C6 Crystal Layout
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ESP32-C6 Series Hardware Design Guidelines v1.0