2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
2.1.2.2 Reset
CHIP_PU serves as the reset pin of ESP32. ESP32 will reset when CHIP_PU is held low and the input level is
below 0.6V and stays for at least 200 µs. To avoid reboots caused by external interferences, the CHIP_PU trace
should be as short as possible and routed away from the clock lines. A pull-up resistor and a ground capacitor
are highly recommended.
Notice:
CHIP_PU pin must not be left floating.
2.1.3 Flash
ESP32 can support up to four 16 MB external QSPI flash and SRAM chips. The demo flash used currently is an
SPI flash with 4 MB ROM, in an SOP8 (208 mil) package. The VDD_SDIO acts as the power supply pin. Make
sure you select the appropriate flash according to the power voltage on VDD_SDIO. Users can add a serial resistor
to Pin21 SD_CLK and connect it to the flash CLK pin.
GPIO19
VDD3P3_CPU
GPIO23
GPIO18
SD_DATA_1
SD_DATA_0
SD_CLK
SD_CMD
SD_DATA_3
SD_DATA_2
GPIO17
VDD_SDIO
GPIO16
ESP32_5x5
2.1.4 Crystal Oscillator
There are two clock sources for the ESP32, that is, an external crystal oscillator clock source and an RTC clock
source.
2.1.4.1 External Clock Source (Compulsory)
In circuit design, capacitors C1 and C2 which connect to the ground are added to the input and output terminals
of the crystal oscillator respectively. The specific capacitive values depend on further testing of, and adjustment
to, the overall performance of the whole circuit. It is recommended that users reserve a series resistor of 0Ω on
the XTAL_P clock trace. Note that the accuracy of the selected crystal is ± 10 PPM.
Espressif Systems
GND
C4
VDD33
0.1uF
38
GPIO19
37
36
GPIO23
35
GPIO18
34
GPIO5
GPIO5
33
SDI/SD1
32
SDO/SD0
31
SCK/CLK
30
SCS/CMD
29
SWP/SD3
28
SHD/SD2
27
GPIO17
26
25
GPIO16
C18
VDD_SDIO
1uF
GND
Figure 4: ESP32 Flash
VDD_SDIO
SCS/CMD
1
/CS
DI
SCK/CLK
6
CLK
DO
SHD/SD2
7
/HOLD
/WP
U3
FLASH
GND
10
ESP32 Hardware Design Guidelines V2.1
5
SDI/SD1
2
SDO/SD0
3
SWP/SD3
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