Power Supply - Espressif Systems ESP32-C6 Series Hardware Design Manuallines

3 PCB Layout Design

3.3 Power Supply

Figure 17: ESP32-C6 Power Traces in a Four-layer PCB Design
• Four-layer PCB design is preferred. The power traces should be routed on inner third layer whenever
possible. Vias are required for the power traces to go through the layers and get connected to the pins on
the top layer. There should be at least two vias if the main power traces need to cross layers. The drill
diameter on other power traces should be no smaller than the width of the power traces.
• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 17. The width of the main
power traces should be no less than 25 mil. The width of the power traces for VDDA3P3 pins should be no
less than 20 mil. Recommended width of other power traces is 10 mil.
• The ESD protection diode is placed next to the power port (circled in red in the top left quarter of Figure 17).
The power trace should have a 10 µF capacitor on its way before entering into the chip, and a 0.1 or 1 µF
capacitor could also be used in conjunction with this 10 µF capacitor. After them, the power traces are
divided into several branches using a star-shape topology, which reduces the coupling between different
power pins. Note that all decoupling capacitors should be placed close to the corresponding power pin,
and ground vias should be added close to the capacitor's ground pad to ensure a short return path.
Notice:
The analog power pin VDDA3P3 are close to the chip's power entrance as shown in Figure
entrance is the starting point of VDD33 highlighted in yellow), so we only use one 10 µF capacitor at VDDA3P3 and
the power entrance. If they are not close to each other, please add one 10 µF capacitor at VDDA3P3, and another
10 µF capacitor at the power entrance. If space allows, please also reserve two 1 µF capacitors.
• As shown in Figure 18, it is recommended to connect the capacitor to ground in the CLC filter circuit near
VDDA3P3 to the fourth layer through a via, and maintain a keep-out area on other layers. The purpose is to
further reduce harmonic interference.
• VDDA3P3 should be surrounded by grounding copper on both sides, and isolated by GND from the RF
and GPIO traces nearby. Vias should be placed whenever possible.
Espressif Systems 22
Submit Documentation Feedback
17 (in Figure
ESP32-C6 Series Hardware Design Guidelines v1.0
17 the power