Power-Up And Reset Timing; Flash; Description Of Timing Parameters For Power-Up And Reset; Visualization Of Timing Parameters For Power-Up And Reset - Espressif Systems ESP32-C6 Series Hardware Design Manuallines

2 Schematic Checklist
Notice:
CHIP_PU pin must not be left floating.

2.2.3 Power-up and Reset Timing

Figure 5 shows the power-up and reset timing of ESP32-C6 series of chips. Details about the parameters are
listed in Table 1.
VDDA3P3,
VDDPST1,
VDDPST2,
VDDA1,
VDDA2
CHIP_PU
Figure 5: Visualization of Timing Parameters for Power-up and Reset
Table 1: Description of Timing Parameters for Power-up and Reset
Parameter Description
Time reserved for the power rails of VDDA3P3, VDDPST1, VD-
t DPST2, VDDA1 and VDDA2 to stabilize before the CHIP_PU pin
ST BL
is pulled high to activate the chip
Time reserved for CHIP_PU to stay below V
t
RST
chip
Notice:
If your device needs to be frequently powered on and off, the power supply ramps up slowly, or the power supply such as
solar photovoltaic is not stable, adding a single RC circuit might not meet the requirements for power-up and reset timing,
and consequently the chip will not boot correctly. In this case, it is advised to take other approaches, such as adding an
external reset chip or a watchdog timer IC. For chips with a 3.3 V flash, the reset threshold is suggested to be around 3.0
V.

2.3 Flash

ESP32-C6 series in QFN40 package can support up to 16 MB external flash, powered by VDD_SPI. It is
recommended to add a zero-ohm series resistor on the SPI lines as shown in Figure 6, to lower the driving
current, reduce interference to RF, adjust timing, and better shield from interference.
ESP32-C6 series of chips in QFN32 package have in-package SPI flash. The pins for flash are not bonded out.
Espressif Systems
t
ST BL
2.8 V
V
IL_nRST
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t
RST
to reset the
IL_nRST
10
ESP32-C6 Series Hardware Design Guidelines v1.0
Min (µs)
50
50