Espressif Systems ESP32-C6 Series Hardware Design Manuallines page 13

C14 TBD
2 Schematic Checklist
Figure 9 shows the schematic of the external signal.
The external signal can be input to the XTAL's P end through a DC blocking capacitor (about 20 pF). The XTAL's
N end can be floating. The signal should meet the following requirements:
Input to XTAL's P End
Sine wave or square wave
2.5 RF
The RF circuit of the ESP32-C6 series of chips is mainly composed of three parts, the RF traces on the PCB
D
board, the chip matching circuit, the antenna and the antenna matching circuit.
For the RF traces on the PCB board, 50 Ω impedance control is required.
Chip matching circuit must be placed close to the chip. It is mainly used to adjust the impedance point and
suppress harmonics. The CLC structure is preferred, and a set of LC can be added if space permits. The CLC
matching circuit is shown in Figure 10.
For the antenna and the antenna matching circuit, to ensure the radiation performance, the antenna's
characteristic impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is
recommended to adjust the antenna. However, if the available space is limited and the antenna impedance point
C
can be guaranteed to be 50 Ω by simulation, then there is no need to add a matching circuit near the
5
antenna.
B
Figure 11 shows the general process of RF tuning. Please be noted the matching parameters are subject to the
RF tuning of PCB board, which depends greatly on the antenna and PCB layout. The initial value of the resistor
can be 0 Ω. For ESP32-C6 series of chips, it is recommended to set the S11 parameter in the figure below to
30+j0 Ω and the center frequency is 2442 MHz.
If the RF function is not required, the RF pin can be left floating.
A
Espressif Systems
CLK_32K C18 TBD
Figure 9: Schematic for ESP32-C6's External Oscillator
5
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB board. The initial value could be
24 nH.
VDD33
C3
1uF
VDD33
GND
L1
C6 C7 C8
10uF 1uF 0.1uF
GND GND GND
ANT1
1 RF_ANT
L2
2
C11
PCB_ANT
TBD
GND GND
The values of C11, L2 and C12
vary with the actual PCB board.
Figure 10: Schematic for RF Matching
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5
1
ANT
2
VDDA3P3
3
VDDA3P3
4
CHIP_EN
5
VDDPST1
GPIO0 6
XTAL_32K_P
7
XTAL_32K_N
8
GPIO2
9
GPIO3
10
MTMS
U1
Amplitude (Vpp, unit: V)
4
0.6 < Vpp < VDD
C2
10nF
GND
2.0nH
C9
4 0.1uF
GND
LNA_IN
TBD
C12
CHIP_EN
TBD
GPIO0
GPIO1
GPIO2
GND
GPIO3
GPIO4
VDD33
C15
0.1uF
GND
13
ESP32-C6 Series Hardware Design Guidelines v1.0
4
GND
GND
Y1
C1
TBD
GND
40MHz(±10ppm)
GND
1
ANT
2
VDDA3P3
3
VDDA3P3
4
CHIP_EN
5
VDDPST1
6
XTAL_32K_P
7
XTAL_32K_N
8
GPIO2
9
GPIO3
10
MTMS
U1
0.1u
30
U0RXD
29 R3
U0TXD
28
VDDPST2
27
GPIO15
26 R1
SPID
25 R1
SPICLK
24 R1
SPIHD
23
VDD_SPI
22 R1
SPIWP
21 R1
SPIQ
C16
0.1u
ESP32-C6
GND
3
GND
C4
TBD
R17 0
GND
3 C10
0.1uF
30
U0RXD
29 R3
U0TXD
28
VDDPST2
27
GPIO15
26 R16
SPID
25 R15
SPICLK
24 R14
SPIHD
23
VDD_SPI
22
R13
SPIWP
21
R10
SPIQ
C16
0.1uF
ESP32-C6
GND
3