Crystal - Espressif Systems ESP32-C3 Series Hardware Design Manuallines

3 PCB Layout Design
• As shown in Figure 15, an ESD protection diode is placed close to the power port (marked in red circle). A
10 µF capacitor is required before the power trace is connected to the ESP32-C3 family chip, to be used in
conjunction with a 0.1 µF capacitor. Then the power traces are divided into two ways from here and form a
star-shape topology, thus reducing the coupling between different power pins. Note that all decoupling
capacitors should be placed close to the power pin, and ground vias should be added close to the ground
pin of decoupling capacitors to ensure a short return path.
• The power supply for the PA is provided by pin 2 and pin 3. It is required to add GND isolation between this
power trace and GPIO traces on the left, and place ground vias as much as possible.
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.
Note:
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a
nine-grid on the EPAD, cover gaps with ink, and place ground vias in the gaps, as shown in Figure 15. This can avoid tin
leakage when you solder the EPAD to the base board.

3.4 Crystal

Figure 17 shows the reference design of the crystal. In addition, the following should be noted:
• The crystal should be placed far from the clock pin to avoid its impact on the chip. It is good practice to
surround the crystal traces with ground copper on all sides and dense ground vias for better isolation.
• There should be no via for the clock input and output traces, which means the traces cannot cross layers.
• The external regulating capacitor should be placed near the left or right side of the crystal, and at the end of
the clock trace whenever possible, to make sure the ground pad of the capacitor is close to that of the
crystal.
• Do not route high-frequency digital signal traces under the crystal. Ideally do not to route any signal trace
under the crystal. Vias on the power traces on both sides of the crystal clock trace should be placed as far
away from the clock trace as possible, and the clock trace should be surrounded by grounding copper on
both sides.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause
interference (e.g. large inductance component), and ensure that around the crystal is a clean large ground
plane.
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ESP32-C3 Family Hardware Design Guidelines V0.5