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GOWIN GW5A Series Schematics

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GW5A series of FPGA Products
Schematic Manual
UG987-1.2E, 04/18/2024

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Summary of Contents for GOWIN GW5A Series

  • Page 1 GW5A series of FPGA Products Schematic Manual UG987-1.2E, 04/18/2024...
  • Page 2 Copyright © 2024 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is a trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 04/20/2023 1.0E Initial version published. 05/06/2023 1.0.1E The pin “DIN” updated to “MISO” in MSPI mode.  “Figure 2-1 Isolate Wave Filtering” in “2.5 Schematic Design Considerations” updated.  “Figure 3-1 RECONFIG_N, READY, DONE Schematic Reference 05/25/2023 1.0.2E Circuit”...

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ..................1 1.4 Support and Feedback ....................... 2 2 Power Supply ....................

  • Page 5: Contents

    Contents 7 Pinout ......................23 UG987-1.2E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 Isolate Wave Filtering ....................... 4 Figure 2-2 Isolate with Ferrite Beads ....................5 Figure 3-1 RECONFIG_N, READY, DONE Schematic Reference Circuit ......... 7 Figure 3-2 EMCCLK and CCLK Diagram ..................9 Figure 4-1 Connection Diagram for JTAG Configuration Mode ............12 Figure 4-2 Connection Diagram for MSPIx1 Configuration Mode .............
  • Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................1 Table 2-1 Arora V FPGA Products Voltage ..................3 Table 2-2 Power Supply Ramp Rate ....................4 Table 2-3 Recommendations for Power Combination ............... 4 Table 3-1 RECONFIG_N, READY, DONE Description ..............6 Table 3-2 CFGBVS Description ......................

  • Page 8: About This Guide

    About This Guide 1.1 Purpose This manual describes the characteristics and special features of GW5A series of FPGA products and provides a comprehensive checklist to guide design processes. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website.

  • Page 9: Support And Feedback

    Serial Peripheral Interface SSPI Slave Serial Peripheral Interface 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Power Supply

    2 Power Supply 2.1 Overview Power Supply 2.1 Overview GW5A series of FPGA products consist of two groups of voltage, as shown in Table 2-1. Table 2-1 Arora V FPGA Products Voltage Group Name Description Core voltage VCCX Auxiliary voltage...

  • Page 11: Power-On Time And Sequence

    If the power-on time is less than 0.2ms, it is recommended that the capacitance be increased to prolong the power-on time. 2.5 Schematic Design Considerations 1. GW5A series of FPGA products need to isolate the wave filtering for each voltage, as shown in Figure 2-1. Figure 2-1 Isolate Wave Filtering FB is a ferrite bead, C1, C2, C3 are ceramic capacitors with accuracy not less than ±10%.

  • Page 12: Figure 2-2 Isolate With Ferrite Beads

    2 Power Supply 2.5 Schematic Design Considerations Group Name Recommendations for Power Combination With current requirements met, you can consider M0_VDDD combining it with M0_VDDA and M_VDD power supplies. With current requirements met, you can consider M0_VDDX combining power supplies that are consistent with the supply voltage.

  • Page 13: Key Configuration Pins

    3 Key Configuration Pins 3.1 READY, RECONFIG_N, DONE Key Configuration Pins 3.1 READY, RECONFIG_N, DONE 3.1.1 Overview Table 3-1 RECONFIG_N, READY, DONE Description Name Description Active low is used as the reset function for the FPGA programming configuration. FPGA can't be configured if RECONFIG_N is set to low.

  • Page 14: Figure 3-1 Reconfig_N, Ready, Done Schematic Reference Circuit

    3 Key Configuration Pins 3.1 READY, RECONFIG_N, DONE Name Description to take DONE signal into account. As a GPIO, it can be used as an input or output pin. If DONE is used as an input GPIO, the initial value of DONE should be 1 before configuring.

  • Page 15: Cfgbvs

    3 Key Configuration Pins 3.2 CFGBVS 3.2 CFGBVS 3.2.1 Overview Table 3-2 CFGBVS Description Name Description CFGBVS (Configuration Banks Voltage Select) is an input pin. The bank where the configuration IO (JTAG, MSPI, etc.) is located refers to bank3, bank4, and bank10.

  • Page 16: Emcclk

    3 Key Configuration Pins 3.4 EMCCLK 3.4 EMCCLK 3.4.1 Overview Table 3-4 EMCCLK Description Name Description Used to configure the optional external clock input source in a master mode (versus the internal configuration oscillator). I, internal  For master mode: FPGA can optionally switch to EMCCLK weak pull- use EMCCLK as the clock source rather than...

  • Page 17: Configuration Mode

    4 Configuration Mode 4.1 Configuration Mode Selection Signal (MODE) Configuration Mode 4.1 Configuration Mode Selection Signal (MODE) 4.1.1 Overview MODE (MODE0, MODE1, MODE2) is GowinCONFIG configuration mode selection signal. When the FPGA powers on or a low pulse triggers the RECONFIG_N, the device enters the corresponding GowinCONFIG state according to the MODE value.

  • Page 18: Jtag

    4Configuration Mode GW5A series of FPGA products will automatically turn to SSPI mode after the program is loaded successfully. If SSPI mode is not used, make sure that SSPI_HOLDN has a pull-down resistor or SSPI_CSN has a pull- up resistor.

  • Page 19: Mspi

    4Configuration Mode 4.2.3 JTAG Circuit Reference Figure 4-1 Connection Diagram for JTAG Configuration Mode 4.7K VCC3P3 JTAG 0.1uF VCC3P3 I/O1 I/O4 I/O2 I/O3 SP3003_04XTG Note! The clock frequency for JTAG configuration mode cannot be higher than 100MHz. 4.3 MSPI 4.3.1 Overview In MSPI (Master SPI) mode, FPGA is as a Master and reads bitstream data from the external Flash via SPI interface to complete configuration.

  • Page 20: Figure 4-2 Connection Diagram For Mspix1 Configuration Mode

    4Configuration Mode 4.3.3 Circuit Reference The connection diagram for configuring Gowin FPGA products through MSPI is shown in Figure 4-2 ~ Figure 4-4. Figure 4-2 Connection Diagram for MSPIx1 Configuration Mode Figure 4-3 Connection Diagram for MSPIx2 Configuration Mode Figure 4-4 Connection Diagram for MSPIx4 Configuration Mode...

  • Page 21: Sspi

    4Configuration Mode 4.4 SSPI 4.4.1 Overview In SSPI (Slave SSPI) mode, FPGA is a slave device and is configured via SPI interface by an external Host. 4.4.2 Signal Definition Table 4-4 Signal Definition of SSPI Configuration Mode Name Description As a configuration pin, it is an input pin with internal weak pull-up.

  • Page 22: Figure 4-5 Connection Diagram For Sspi Configuration Mode

    4Configuration Mode 4.4.3 Circuit Reference The connection diagram for configuring Gowin FPGA products via SSPI is shown in Figure 4-5. Figure 4-5 Connection Diagram for SSPI Configuration Mode Note! This figure is the connection diagram for SSPI configuration mode. The connection diagram for configuring multiple FPGA products via SSPI is shown in Figure 4-6.

  • Page 23: Cpu

    In Master CPU mode (i.e. FPGA is the master device), the configuration data is read from the external via the DBUS interface for configuration. In Slave CPU mode, GW5A series of FPGA products are configured by external Host via DBUS interface. 4.5.2 Signal Definition...

  • Page 24: Serial

    Power-on again or trigger RECONFIG_N at one low pulse. 4.6 SERIAL 4.6.1 Overview In SERIAL configuration mode, Host configures Gowin FPGA products through the serial interface. SERIAL is one of the configuration modes that use the least number of pins. It supports both master mode and slave mode.

  • Page 25: Figure 4-8 Connection Diagram For Serial Configuration Mode

    4Configuration Mode 4.6.2 Signal Definition Table 4-6 Signal Definition of SERIAL Configuration Mode Name Description As a configuration pin, it is an input pin. It is a serial data input pin.  In SERIAL and MSPI modes: DIN receives serial data from I, internal the data source and samples data at the CCLK rising edge in weak pull-up...

  • Page 26: Clock Pin

    DS1103, GW5A series of FPGA Products Data Sheet  GCLK: The GCLK is distributed as 8 clock regions in GW5A series of FPGA products. Each Clock provides 16 GCLKs. The clock sources of GCLK can be from dedicated clock pins, the output of the PLL, the output of HCLK, and common wiring resources.

  • Page 27: Table 5-1 Clock Overview

    5Clock Pin Table 5-1 Clock Overview Name Overview Dedicated clock input pin driving the same clock region, T SGCLKT_[x] (True), [x]: clock No. SGCLKC_[x] Differential input pin of SGCLKT_[x], C (Comp), [x]: clock No. Dedicated clock input pin driving multiple clock region, T (True), MGCLKT_[x] [x]: clock No.

  • Page 28: Schematic Design Considerations

    5Clock Pin 5.2 Schematic Design Considerations 1. System clock pins selection: GCLK is directly connected to all resources in the device. The GCLK_T end is advised if the GCLK inputs from the single-end. If the external clock as a PLL clock input, it is advised to input from the PLL dedicated pin.

  • Page 29: Differential Pins

    Different packages employ different signals. Please refer to the True LVDS section of the Package Pinout Manual for further details. 3. Schematic Design Considerations All banks of GW5A series of FPGA products support true differential input. The differential input requires an external 100 ohm termination resistor, which is laid out on the PCB as close as possible to the input pins.
  • Page 30 I/O LOGIC, global clock resources, PLL resources, etc. All banks of the GW5A series of FPGA products support true LVDS output, please refer to GW5A series of FPGA Product Pinout to ensure that the corresponding pins support true LVDS output.

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