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GOWIN GW2AN-18X Programming And Configuration Manual

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GW2AN-18X & 9X
Programming and Configuration Guide
UG702-1.1E, 09/06/2022

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  • Page 1 GW2AN-18X & 9X Programming and Configuration Guide UG702-1.1E, 09/06/2022...
  • Page 2 Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 09/10/2021 1.0E Initial version published. 03/04/2022 1.0.1E The default states of configuration pins updated. 07/28/2022 1.0.2E Note about I C configuration mode added. Section 5.8 I2C Configuration Mode updated. 09/06/2022 1.1E Section 6.5 Background Programming added.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ....................... v 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ..................2 1.4 Support and Feedback ....................... 3 2 Glossary ......................
  • Page 5 5.6 CPU Configuration Mode ....................50 5.6.1 Configuration Timing ..................... 51 5.7 SERIAL ..........................51 5.8 I C Configuration Mode ....................53 5.8.1 Configuration Instruction ....................56 5.8.2 The Process of Configuring SRAM through I C ............57 5.8.3 The Process of Configuring (Programming) Flash through I C ........

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 4-1 Configuring Pin Reuse ..................... 11 Figure 5-1 Recommended Pin Connection ..................17 Figure 5-2 Power Recycle Timing ...................... 17 Figure 5-3 Trigger Timing ........................18 Figure 5-4 Connection Diagram for JTAG Configuration Mode ............20 Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode ........
  • Page 7 Figure 5-34 I C Configuration timing ....................54 Figure 5-35 Reinit Timing Diagram ....................56 Figure 5-36 SRAM Configuration Timing Diagram ................56 Figure 5-37 Flash Configuration Timing Diagram ................57 Figure 5-38 Reboot Timing Diagram ....................57 Figure 5-39 Flow Chart of Configuring SRAM through I C ..............
  • Page 8 Table 5-18 I C Configuration Mode Frequency and Address............. 55 Table 5-19 I C Configuration Instruction .................... 56 Table 6-1 Gowin FPGA GW2AN-18X/9 X Products Configuration File Size (Max.) ......70 Table 6-2 Loading Time in Autoboot Mode ..................71 UG702-1.1E...

  • Page 9: About This Guide

    This guide mainly introduces general features and functions on programming and configuration of the GW2AN-18X/9X device in Arora family. It helps users to use Gowin FPGA products to their full potential. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website. You can find the related documents at www.gowinsemi.com:...

  • Page 10: Terminology And Abbreviations

    Full Name Abbreviations Look-up Table FPGA Field Programmable Gate Array JTAG Joint Test Action Group GPIO Gowin Programmable I/O Serial Peripheral Interface SRAM Static Random Access Memory MSPI Master Serial Peripheral Interface SSPI Slave Serial Peripheral Interface Central Processing Unit...

  • Page 11: Support And Feedback

    1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 12: Glossary

    2 Glossary Glossary This chapter presents an overview of the terms that are commonly used in the process of programming and configuring of Gowin FPGA products to help users get familiar with the related concepts. Table 2-1 Glossary Glossary Meaning...
  • Page 13 Edit Mode output of all GPIOs is high-impedance state, except transparent transmission. Identification for the the Gowin FPGA device. Each series of ID CODE devices has a different number. Used to identify the FPGA device that used. The user code...

  • Page 14: Configuration Modes

    The Arora Family FPGA products support bitstream decompression; users can compress bitstream to save storage memory. 16M-bit Serial Flash (With Quad SPI) is embedded in GW2AN-18X/9X. Up to 100Mhz Quad SPI configuration mode can be supported, and Fixed-Address GOLDEN-IMAGE mode is supported.
  • Page 15 3 Configuration Modes Configuration Modes MODE[1:0] Description interface by external Host. Supports up to 100 Mhz. Supported automatically upon completion of Autoboot or MSPI. FPGA products are configured via I C interface by external Host. The supported frequency is 100KHz~555KHz.. FPGA products are configured via DIN SERIAL interface by external Host.

  • Page 16: Configuration Pin

    4.1 Configuration Pin List and Reuse Options 4.1.1 Configuration Pin List Table 4-1 contains a list of all the configuration pins of Gowin FPGA products together with the details of the pins used in each configuration mode and the shared pins in chip packages.

  • Page 17: Configuration Pin Reuse

    To maximize the utilization of I/O, Gowin FPGA product support for setting the configuration pins as GPIO pins. Before any configuration operation is performed on all series of Gowin FPGA products after power up, all related configuration pins are used as configuration pins by default.
  • Page 18 Configuration Pin Reuse The steps are as follows: 1. Open the project in Gowin software; 2. Select “Project > Configuration > Dual Purpose Pin” from the menu options, as shown in Figure 4-1; 3. Check the corresponding options to set the configuration pins reuse.

  • Page 19: Configuration Pin Function And Application

    4.2 Configuration Pin Function and Application The RECONFIG_N, READY, and DONE pins are used in all configuration modes. Other pins can be set as dedicated pins or GPIO (Gowin Programmable IO) according to their specific application. Table 4-3 Pin Function Pin Name...
  • Page 20 As a configuration pin, it is an input pin with internal weak pull-down. If JTAG pins are set as a GPIO in the Gowin software, the JTAG pins can become GPIOs after the device being powered up and successfully configured.
  • Page 21 4 Configuration Pin 4.2 Configuration Pin Function and Application Pin Name Functional Description It is a serial clock input pin in the JTAG configuration mode. As a GPIO, it can be used as an input or output type. As a configuration pin, it is an input pin with internal weak pull-up. It is a serial input pin in JTAG configuration mode.
  • Page 22 4 Configuration Pin 4.2 Configuration Pin Function and Application Pin Name Functional Description As a configuration pin, it is an output pin. It is a serial data output pin in the SERIAL configuration mode, which DOUT is only used as the input to the latter device when the FPGA is cascading.

  • Page 23: Configuration Mode Introduction

    5.1 Configuration Notes Configuration Mode Introduction GW2AN-18X/9X products are non-volatile devices with built-in flash. Any configuration data that is stored in the SRAM device is lost after it is powered down; as such, it needs to be reconfigured each time it is powered up.
  • Page 24 5 Configuration Mode Introduction 5.1 Configuration Notes with successful ID verification can be configured. The USER CODE is the identification number for users to distinguish between the devices that share the same ID CODE. The state register of the device records the status information before and after FPGA configuration, and you can use this information to analyze the state of the device accordingly.

  • Page 25: Figure 5-1 Recommended Pin Connection

    Note! You can add a DIP switch to change the MODE value. Some MODE pins of devices  are not all bonded out, please refer to UG792, GW2AN-18X Pinout UG978, GW2AN-9X Pinout to get the MODE pin values; The values of READY and DONE signals have no meaningful reference in JTAG ...

  • Page 26: Auto Boot Configuration

    0x000000 of the built-in Flash with the default frequency of 100MHz and QuadSPI protocol. GW2AN-18X/9X supports two AUTO BOOT configurations. That is, when the AUTO BOOT configuration fails after power-on, the device automatically performs the second configuration from the address 0x100000.

  • Page 27: Jtag Configuration

    IEEE1532 standard and the IEEE1149.1 boundary scan standard. The JTAG configuration mode writes bitstream data to the SRAM of Gowin FPGA products. All configuration data is lost after the device is powered down. All Gowin FPGA products support the JTAG configuration mode.

  • Page 28: Connection Diagram For The Jtag Configuration Mode

    The clock frequency for JTAG configuration mode cannot be higher than 65MHz. Gowin FPGA products support JTAG daisy chain operation, which connects the FPGA TDO pin to the next FPGA TDI pin. Gowin programming software will identify the connected FPGA devices automatically and configure them in turn.

  • Page 29: Jtag Configuration Timing

    5 Configuration Mode Introduction 5.3 JTAG Configuration 5.3.3 JTAG Configuration Timing See Table 5-6 for the timing of JTAG mode. Figure 5-6 JTAG Configuration timing See Table 5-3 for the description of timing parameters. Table 5-3 JTAG Configuration Timing Parameters Name Description Min.

  • Page 30: Figure 5-7 Tap State Machine

    5 Configuration Mode Introduction 5.3 JTAG Configuration Figure 5-7 TAP State Machine TAP Reset After TMS keeps high (logic "1") and at least 5 strobes are input (higher and then low) at the TCK terminal, the TAP logic is reset, the TAP state machine in other states is converted into the state of test logic reset, and the JTAG port and the test logic are reset.

  • Page 31: Figure 5-8 Instruction Register Access Timing

    5 Configuration Mode Introduction 5.3 JTAG Configuration Figure 5-8 Instruction Register Access Timing Figure 5-9 Data Register Access Timing Note! The total length of the instruction register is 8 bits;  The length of the data register can vary depending on the selected register. ...

  • Page 32: Table 5-4 Gowin Fpga Device Idcode

    ID Code, i.e. JEDEC ID Code, is a basic identification of FPGA products. The length of the Gowin FPGA ID Code is 32 bits. The ID Codes of the FPGA are listed in the following table. Table 5-4 Gowin FPGA Device IDCODE...

  • Page 33: Figure 5-10 Flow Chart Of Reading Id Code State Machine

    5 Configuration Mode Introduction 5.3 JTAG Configuration Figure 5-10 Flow Chart of Reading ID Code State Machine Start Move TAP to Shift-DR Move TAP to Shift-IR Transfer 32 clocks to get ID Code & Transfer Move TAP to Exit1DR Read ID Code(0x11) instruction (LSB) &...
  • Page 34 FPGA functions. SRAM is configured via JTAG to avoid the influence of Configuration Mode Pins. Generate the FS file using Gowin software. Configure SRAM using JTAG. The process of SRAM configuration using the external Host is as follows, as shown in Figure 5-13.

  • Page 35: Figure 5-13 Sram Configuration Flow

    5 Configuration Mode Introduction 5.3 JTAG Configuration Figure 5-13 SRAM Configuration Flow Check See Read Flow ID Code ReInit (Option) SRAM Erase (Option) Transfer Config Enable Instruction (0x15) Transfer Address Init Instruction (0x12) Transfer Write Instruction (0x17) Transfer Bitstream(MSB) Transfer Config Disable Instruction (0x3A) Transfer...

  • Page 36: Table 5-6 Count Of Address And Length Of One Address

    SRAM. Table 5-6 Count of Address and Length of One Address Device Length of One Address (bits/address) Count of Address GW2AN-18X/9X 3376 1342 The reading process is described in detail below, as shown in Figure 5-14.

  • Page 37: Figure 5-14 Process Of Reading Sram

    5 Configuration Mode Introduction 5.3 JTAG Configuration Figure 5-14 Process of Reading SRAM Start Transfer Config Enable Instruction (0x15) Transfer Initialize Address Instruction (0x12) Transfer Read Instruction (0x03) Next address is valid Read data of one address Compute the checksum(16bit) Transfer Config Disable Instruction (0x3A)
  • Page 38 The reference time for GW2AN-18X/9X is 6ms.  Embedded Flash Programming Modes 16 Mbit Serial Flash is embedded in GW2AN-18X/9X devices. JTAG provides an SPI-like protocol to program the embedded Flash. The maximum operating frequency is 65Mhz. The SPI-like protocol provided by JTAG has the same logic with the standard SPI protocol.
  • Page 39 5 Configuration Mode Introduction 5.3 JTAG Configuration Embedded Flash Instruction -WriteEnable（0x06） WriteEnable (above) is used to set WriteEnable Latch (WEL) bit of Flash Status Register. The WEL bit must be set before each Page -program, Sector Erase, and Chip Erase. When TMS is low and after one clock cycle (TCK), the instruction "0x06"...
  • Page 40 5 Configuration Mode Introduction 5.3 JTAG Configuration dummy clocks, the data of Status Register-1 will be outputted from the TDO pin at the falling edge of TCK, with the most significant bit (MSB) first. As shown in the figure below. Read Status Register-1 contains eight bits, represented by S[7:0].
  • Page 41 5 Configuration Mode Introduction 5.3 JTAG Configuration UG702-1.1E 33(76)
  • Page 42 5 Configuration Mode Introduction 5.3 JTAG Configuration Embedded Flash Instruction - Sector Erase（0x20） Sector Erase is used to erases all data in a specified Sector (4Kbytes). After the erasing is complete, the Flash data is restored to the 0xFF state. The WriteEnable instruction must be completed before sending this instruction.
  • Page 43 5 Configuration Mode Introduction 5.3 JTAG Configuration Flow Chart of Configuring the Embedded Flash start Read Status Code Ready Down ReInit Is Wakeup Erase SRAM Enable Flash Config-mode Chip Erase Page Program loops Disable Flash Config-mode Reconfig FPGA UG702-1.1E 35(76)

  • Page 44: Figure 5-15 Process Of Use Boundary Scan Mode To Program Spi Flash

    5 Configuration Mode Introduction 5.3 JTAG Configuration Program SPI Flash in JTAG Boundary Scan Mode The principle of this mode is changing the state of the pins connected to SPI by using Boundary Scan method to implement SSPI timing, and then to program the internal Flash.

  • Page 45: Table 5-8 Status Register Definition

    0x41 and the timing is the same as that of Read ID Code. The meaning of the Status Register is shown in Table 5-8. Table 5-8 Status Register Definition Device GW2AN-18X/9X Status Register[31:0] CRC Error (1 indicates that an Error occurred and 0 indicates that no Error occurred)

  • Page 46: Sspi

    Read ID Code. The user code adopts the checksum value in the FS file by default. It can be redefined using Gowin Designer. Reload Reconfig 0x3C This instruction is used to read the bitstream files from Flash and write to SRAM.
  • Page 47 5 Configuration Mode Introduction 5.4 SSPI Pin Name Description Internal RECONFIG_N Low level pulse: Start GowinCONFIG weak pull-up I/O, High level: FPGA can be programmed and configured Internal READY weak Low level: Programming configuration for FPGA pull-up is prohibited I/O, High-level: Successfully programmed and configured;...

  • Page 48: Sspi Configuration Timing

    5 Configuration Mode Introduction 5.4 SSPI 5.4.2 SSPI Configuration Timing See Figure 5-17 for the SSPI timing. Figure 5-17 SSPI Configuration Timing See Table 5-10 for the SPPI configuration timing parameters. Table 5-10 SSPI Configuration Timing Parameters Name Description Min. Max.

  • Page 49: Figure 5-18 Read Id Code Timing

    5 Configuration Mode Introduction 5.4 SSPI The SSPI instruction of FPGA is generally composed of 1-4 bytes, including at least 1 instruction class byte and multiple redundant information bytes. If there is no specified information byte, the redundant information byte can be any number (0x00 is used in the following table). Table 5-11 Configuration Instruction Name Complete Instruction (Instruction Byte +...

  • Page 50: Figure 5-19 Write Enable (0X15) Timing

    5 Configuration Mode Introduction 5.4 SSPI Write Enable (0x1500) Before configuring SRAM (write Features), enter programming mode using “Write Enable (0x15)” instruction to receive the “WriteData (0x3B)” write data instructions. Figure 5-19 Write Enable (0x15) Timing Note! At CS high level, more than two clocks should be given to SCLK to drive FPGA to identify CS signal.

  • Page 51: Figure 5-21 Write Data (0X3B) Timing

    5 Configuration Mode Introduction 5.4 SSPI Write Data (0x3B) The fs file is sent directly to the FPGA device using the “WriteData (0x3B)” instruction. Note that CS keeps low level in the process of data writing. Figure 5-21 Write Data (0x3B) Timing UG702-1.1E 43(76)

  • Page 52: Sspi Configure Sram Flow

    5 Configuration Mode Introduction 5.4 SSPI 5.4.4 SSPI Configure SRAM Flow start Read Status Code Ready Down ReInit Is Wakeup Erase SRAM Init Address Write Enable Write Data 0x3B Write Disable UG702-1.1E 44(76)

  • Page 53: Connection Diagram For Sspi Configuration Mode

    The MODE value of the Flash programming is the same as the MODE value of SSPI configuration mode. Configuration data can be written to SRAM or an external Flash using Gowin programmer. Before loading from the external Flash, the MODE value should be adjusted to MSPI MODE, and then the MSPI loading can be triggered by powering on again or triggering RECONFIG_N.

  • Page 54: Multiple Fpga Connection View In Sspi Mode

    5 Configuration Mode Introduction 5.4 SSPI Figure 5-24 The Flow Chart of Flash Configuration via SSPI Start Transfer Program SPI Flash Instruction (0x1600) Program Flash following SPI timing 5.4.6 Multiple FPGA Connection View in SSPI Mode Figure 5-25 Multiple FPGA Connection Diagram 1 UG702-1.1E 46(76)

  • Page 55: Qsspi Configuration Mode

    5 Configuration Mode Introduction 5.5 QSSPI Configuration Mode Figure 5-26 Multiple FPGA Connection Diagram 2 5.5 QSSPI Configuration Mode By default, the Quad Enable Bit(QE) of the embedded Flash is enabled. You can directly use the Quad Slave SPI (QSSPI). The QSSPI configuration pins are shown in Table 5-12.

  • Page 56: Figure 5-27 Qsspi Write Data (0X6B) Timing

    5 Configuration Mode Introduction 5.5 QSSPI Configuration Mode Pin Name Description pull-down Internal (QSSPI_WPN) As IO of Quad SPI weak pull-down Internal (SO) As IO of Quad SPI weak pull-down Internal (SI) As IO of Quad SPI weak pull-down Internal SSPI_CS_N QSSPI Chip selection signal, active low.

  • Page 57: Figure 5-28 The Flow Chart Of Sram Configuration Via Qsspi

    5 Configuration Mode Introduction 5.5 QSSPI Configuration Mode Figure 5-28 The Flow Chart of SRAM Configuration via QSSPI start Read Status Code Ready Down ReInit Is Wakeup Erase SRAM Init Address Write Enable Write Data 0x6B(QSSPI) Write Disable UG702-1.1E 49(76)

  • Page 58: Cpu Configuration Mode

    5 Configuration Mode Introduction 5.6 CPU Configuration Mode 5.6 CPU Configuration Mode In CPU mode, the Host configures Gowin FPGA products through the 8-bit data bus interface. CPU mode pins are shown in Table 5-13. Table 5-13 CPU Mode Pins...

  • Page 59: Configuration Timing

    Figure 5-30 CPU Mode Configuration Timing 5.7 SERIAL In SERIAL mode, Host configures Gowin FPGA products via serial interface. SERIAL is one of the configuration modes that use the least number of pins. The SERIAL mode can only write bitstream data to FPGA and cannot readback data from FPGA devices;...

  • Page 60: Figure 5-31 Connection Diagram For Serial Mode

    5 Configuration Mode Introduction 5.7 SERIAL Pin Name Description pull-up Low level: Programming configuration for device is prohibited High-level: Successfully programmed and I/O, internal configured; DONE weak Low-level: Programming and configuration pull-up uncompleted or failed. I, internal Configuration mode selection, READY rising edge MODE[1:0] weak sampling...

  • Page 61: I 2 C Configuration Mode

    Power-on again or trigger RECONFIG_N at one low pulse. 5.8 I C Configuration Mode In I C Mode, Gowin FPGA products are configured by Host via I2C interface. I C is one of the configuration modes that use the least number of pins. The I C mode can only write bitstream data to FPGA and cannot readback data from FPGA devices;...

  • Page 62: Figure 5-33 Connection Diagram For I C Configuration Mode

    The figure above shows the minimum system diagram of the I C MODE. Figure 5-1 shows the other fixed pin connections.  GW2AN-18X/9X do not support standard I C bus, they only support single device configuration based on I2C protocol. Figure 5-34 I C Configuration timing C is a serial transmission bus.

  • Page 63: Table 5-18 I 2 C Configuration Mode Frequency And Address

    The level on the SDA is allowed to change state only while the SCL is low. Logic 0 has a low voltage level and Logic 1 has a high voltage level.As shown in the figure below. The list of I2C mode supported by Gowin FPGA devices is as shown in Table 5-18. Table 5-18 I...

  • Page 64: Configuration Instruction

    5 Configuration Mode Introduction 5.8 I2C Configuration Mode 5.8.1 Configuration Instruction The I C configuration mode uses a uniform address and uses different instructions to specify the configuration of SRAM or Flash. The following is a list of I C instructions: Table 5-19 I C Configuration Instruction Name...

  • Page 65: The Process Of Configuring Sram Through I C

    5 Configuration Mode Introduction 5.8 I2C Configuration Mode Figure 5-37 Flash Configuration Timing Diagram Figure 5-38 Reboot Timing Diagram Reboot/reconfig ADDRESS 5.8.2 The Process of Configuring SRAM through I The process of configuring SRAM through I C is as follows: 1.

  • Page 66: The Process Of Configuring (Programming) Flash Through I

    5 Configuration Mode Introduction 5.8 I2C Configuration Mode Figure 5-39 Flow Chart of Configuring SRAM through I start I2c_send_start &send i2c_slave_addr(7bit) I2c_Send config sram I2c_send_start &send cmd（0x33） i2c_slave_addr(7bit) I2c_Send fs data （MSB） I2c_Send reinit cmd （0x3f） I2c_send_stop I2c_send_stop 5.8.3 The Process of Configuring (Programming) Flash through I The data form of configuring Flash through I C is as follows: ------- SPI value...

  • Page 67: Figure 5-40 Flow Chart Of Erasing Flash Through I 2 C

    5 Configuration Mode Introduction 5.8 I2C Configuration Mode Figure 5-40 Flow Chart of Erasing Flash through I C： I2c_send_start &send i2c_slave_addr(7bit) start I2c_Send config flash cmd（0x55） I2c_send_start &send Erase flash i2c_slave_addr(7bit) I2c_Send 0x00 (cs is high) I2c_Send reinit cmd I2c_Send 0x06 & （0x3f）...

  • Page 68: Figure 5-41 Flow Chart Of Configuring Flash Through I 2 C

    5 Configuration Mode Introduction 5.8 I2C Configuration Mode 14. Send data 0x00 (pull up the CS signal); 15. Send the stop signal; 16. Repeat steps 5-15 until the data stream file writing is completed; 17. Send the start signal and 7-bit address (write operation); 18.

  • Page 69: Bitstream File Configuration

    6 Bitstream File Configuration 6.1 Configuration Options Bitstream File Configuration The features of Gowin FPGA products need to be configured and programmed using Gowin software. The settings mainly include configuration pins multiplexing options and bitstream data configuration options. This chapter describes the bitstream file configuration. For the details about the configuration pin reuse, please refer to 4.1.2...

  • Page 70: Configure Data Encryption

    Figure 6-1 Configuration Options Note! The security bit setting is forcibly checked after Gowin software verifies the encryption key setting option. In addition to ensuring the data is secure during the transmission process, using these bitstream settings during configuration also prevents any readback, thereby ensuring maximum protection of user data.

  • Page 71: Enter Encryption Key

    Key. This operation is named as "lock" in this manual. When it's locked, all the read back data is 1. 6.2.2 Enter Encryption KEY Refer to the steps below to write the encryption keys in Gowin software: 1. Open the corresponding project in Gowin software;...

  • Page 72: Programming Operation

    Note! The initial value of the Gowin FPGA keys is 0. If a key value is changed to 1, it cannot be changed back to 0. For example, the key value written during an operation is 00000000-00000000-00000000-00000001, and the last bit of the modified key must be 1.

  • Page 73: Figure 6-4 Aes Security Configure

    6 Bitstream File Configuration 6.2 Configure Data Encryption Figure 6-4 AES Security Configure This configuration contains the following three parts: Write: Write Key;  Read: Read Key;  Lock: Lock read and write access to the Key.  Write 1. Write the user-defined Key to the text box in the figure above; 2.

  • Page 74: Programming Flow

    6 Bitstream File Configuration 6.2 Configure Data Encryption 6.2.5 Programming Flow Figure 6-5 ~ Figure 6-8 show the flow of how to program or Lock the AES key. All the flows are based on JTAG protocol. Check IDCODE Check the device ID to determine whether the JTAG protocol works properly and whether the programing object is correct to avoid misoperation.

  • Page 75: Figure 6-6 Read Aes Key Flow

    6 Bitstream File Configuration 6.2 Configure Data Encryption Read AES Key Figure 6-6 Read AES Key Flow Transmit ISC Enable Command (0x15) Transmit Read Key Command (0x25) Read 128 Bits Transmit ISC Disable Command (0x3A) Stop UG702-1.1E 67(76)

  • Page 76: Figure 6-7 Program Aes Key Flow

    6 Bitstream File Configuration 6.2 Configure Data Encryption Program AES Key Figure 6-7 Program AES Key Flow Transmit ISC Enable Command (0x15) Transmit Program EFuse Command (0x24) Transmit Program Key Command (0x29) Transmit 128bits Delay 800 ms Transmit Read ID Command ( 0x11) Transmit ISC Disable Command (0x3A)

  • Page 77: Configuration File Size

    Stop 6.3 Configuration File Size The Gowin bitstream format can be Text (ASCii) with annotations or Binary with no annotations. The file with a .fs suffix is a text format file. Lines beginning with “//” are annotations. The others is the bitstream data.

  • Page 78: Figure 6-9 Bitstream Format Generation

    Gowin supports compressing bitstream data. The compression ratio is related to the user design. This manual only provides uncompressed configuration file sizes, as shown in Table 6-1. Table 6-1 Gowin FPGA GW2AN-18X/9 X Products Configuration File Size (Max.) Max. Configuration File Size 8,640...

  • Page 79: Configuration File Loading Time

    6.4 Configuration File Loading Time 6.4 Configuration File Loading Time Gowin FPGA can be used as Master to read bitstream files from Flash and configure SRAM, including Autoboot mode and MSPI mode. In Autoboot mode, FPGA reads bitstream files from internal Flash. In MSPI mode, FPGA reads bitstream files from external Flash.

  • Page 80: Background Programming

    QMSPI Mode: = POR time + Number of Data Stream Bits / Clock Cycle loading time The POR time for GW2AN-18X/9X is about 6.3 ms. 6.5 Background Programming Background programming allows you to upgrade data files in Flash without affecting the current operation. The IO states can be maintained when a new data stream file is being loaded.

  • Page 81: Safety Precautions

    GOWINSEMI products have specific IDs that distinguish them from the other series of products. The bitstream generated by Gowin Software contains an ID verification directive, as such, users only need to select the specific device when creating a new project.
  • Page 82 After configuration, the device bitstream will be loaded to the SRAM or on-chip Flash according to the user mode selected. If the data is loaded to the SRAM, Gowin software will set the security  bit automatically in the process of bitstream generation, and no user can read SRAMs.

  • Page 83: Boundary Scan

    To perform a boundary scan, follow the steps outlined below: 1. Connect the FPGA development board to the PC and then power up; 2. Open Gowin programmer and scan the connected devices; 3. Double-click in the "Operation" field and select "External Flash Mode”...

  • Page 84: Figure 8-1 Boundary Scan Operation Schematic Diagram

    8 Boundary Scan Figure 8-1 Boundary Scan Operation Schematic Diagram The boundary scan operation can only be performed on the external Flash of FPGA and cannot be used to program the embedded Flash or SRAM. This operation is irrelevant with the FPGA MODE value, but it is slower than that of the external Flash programming via JTAG.

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