Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for GOWIN DK_START_GW2AR-LV18EQ144PC8I7
Summary of Contents for GOWIN DK_START_GW2AR-LV18EQ144PC8I7
- Page 1 DK_START_GW2AR-LV18EQ144PC8I7_V1. User Guide DBUG405-1.0E, 09/06/2021...
- Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 09/06/2021 1.0E Initial version published.
-
Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Description .............. - Page 5 3.9.1 Overview ........................19 3.9.2 LVDS Circuit ........................19 3.9.3 Pinout ..........................20 3.10 Ethernet .......................... 21 3.10.1 Overview ........................21 3.10.2 Ethernet Circuit ......................21 3.10.3 Pinout ........................... 22 4 Considerations .................... 24 5 Gowin Software ................... 25 DBUG405-1.0E...
-
Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_START_GW2AR-LV18EQ144PC8I7_V1.1 Development Board ....... 3 Figure 2-2 A Development Board Kit ....................4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Architecture ......................5 Figure 3-1 Connection Diagram for FPGA USB Downloading ............10 Figure 3-2 Power System Distribution .................... - Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminologies ..................2 Table 2-1 Development Board Specification ..................7 Table 3-1 FPGA Download and Pinout ....................10 Table 3-2 FPGA Power Pinout ......................12 Table 3-3 FPGA Clock and Reset Pinout ................... 13 Table 3-4 LED Pinout .........................
-
Page 8: About This Guide
DS226, GW2AR series of FPGA Products Data Sheet UG229, GW2AR series of FPGA Products Package and Pinout UG113, GW2AR-18 Pinout UG290, Gowin FPGA Products Programming and Configuration User Guide SUG100, Gowin Software User Guide 1.3 Abbreviations and Terminology The abbreviations and terminology used in this manual are as shown in Table 1-1 below. -
Page 9: Support And Feedback
Phase-locked Loop Delay-locked Loop EQ144 EQFP144 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com... -
Page 10: Development Board Description
2 Development Board Description 2.1 Overview Development Board Description 2.1 Overview Figure 2-1 DK_START_GW2AR-LV18EQ144PC8I7_V1.1 Development Board DK_START_GW2AR-LV18EQ144PC8I7_V1.1 development board adopts the GW2AR-18 device. 64Mbit PSRAM is embedded in this device. The GW2AR series of FPGA products are the first generation products of the Arora ®... -
Page 11: A Development Board Suite
2 Development Board Description 2.2 A Development Board Suite 2.2 A Development Board Suite A development board suite includes the following items: DK_START_GW2AR-LV18EQ144PC8I7_V1.1 development board USB cable Figure 2-2 A Development Board Kit ① DK_START_GW2AR-LV18EQ144PC8I7_V1.1 development board ② USB Cable DBUG405-1.0E 4(25) -
Page 12: Pcb Components
2 Development Board Description 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components GPIO GPIO 1.0V 1.8V Mode Control Power GPIO on/off 5V IN FPGA Download 3.3V LVDS FPGA Ethernet Switches LVDS Ethernet GPIO GPIO FLASH Reset 2.4 System Architecture Figure 2-4 System Architecture 2*BUTTON 2*SWITCH... -
Page 13: Features
2 Development Board Description 2.5 Features 2.5 Features The structure and features of the development board are as follows: 1. FPGA EQFP144 package Up to 120 user I/O Abundant LUT4 resources Multiple modes and capacities of BSRAM ... -
Page 14: Development Board Specification
2 Development Board Description 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functions Technical Conditions Note FPGA Core chip – – Support an USB interface; Support USB-JTAG module on Download – JTAG, MSPI, and board Multi BOOT Input power: 5V... - Page 15 2 Development Board Description 2.6 Development Board Specification Item Functions Technical Conditions Note outlet; 2A self-recovery fuses are connected at power inlet Voltage – Input Voltage: 5V – Humidity – – Temperature – Operating range: –20°~70° – DBUG405-1.0E 8(25)
-
Page 16: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW2AR series of FPGA Products, please refer to DS226, GW2AR series of FPGA Products Data Sheet. I/O BANK Introduction For the I/O BANK, package and pinout information, please refer to UG229, GW2AR series of FPGA Products Package and Pinout. -
Page 17: Usb Download Circuit
3 Development Board Circuit 3.2 Download 3.2.2 USB Download Circuit Figure 3-1 Connection Diagram for FPGA USB Downloading 3.2.3 Download Flow 1. FPGA SRAM Download Mode: Plug the USB cable to the USB interface (J26) on the development board. Power on. Open the Programmer, select SRAM mode, and then select the bitstream file you required. -
Page 18: Power Supply
3 Development Board Circuit 3.3 Power Supply 3.3 Power Supply 3.3.1 Overview DC5V is input by USB interface. The TI LDO power supply chip is used to step down voltage from 5V to 3.3V, 1.8V and 1.0V, which can meet the power demand of the development board. -
Page 19: Fpga Power Pinout
3 Development Board Circuit 3.4 Clock, Reset 3.3.3 FPGA Power Pinout Table 3-2 FPGA Power Pinout Signal Name Pin No. BANK Description VCCO0 I/O Bank Power 3.3V VCCO1 I/O Bank Power 3.3V VCCO2 I/O Bank Power 1.8V VCCO3 77, 91 I/O Bank Power 3.3V VCCO4... -
Page 20: Clock, Reset
3 Development Board Circuit 3.5 LED 3.4.2 Clock, Reset Figure 3-3 Clock, Reset 3.4.3 Pinout Table 3-3 FPGA Clock and Reset Pinout Signal Name Pin No. BANK Description FPGA_CLK 50MHz crystal oscillator Input 3.3V FPGA_RST_N Reset signal, active low 1.8V 3.5 LED 3.5.1 Overview Four green LEDs are incorporated into the development board and are... -
Page 21: Pinout
3 Development Board Circuit 3.6 Switches 3.5.3 Pinout Table 3-4 LED Pinout Signal Name Pin No. BANK Description F_LED1 LED1 3.3V F_LED2 LED2 3.3V F_LED3 LED3 3.3V F_LED4 JESD 4 3.3V 3.6 Switches 3.6.1 Overview Two Slide switches are incorporated into the development board. These are used to input the 0/1 signal during testing. -
Page 22: Key
3 Development Board Circuit 3.7 Key 3.7 Key 3.7.1 Overview Two key switches are embedded in the development board. Users can manually input the 0/1 signal to the corresponding FPGA pins for testing purposes. Press the key to input 0; Input 1 when the key is up. 3.7.2 Key Circuit Figure 3-6 Key Circuit 3.7.3 Pinout... -
Page 23: Gpio Circuit
3 Development Board Circuit 3.8 GPIO 3.8.2 GPIO Circuit Figure 3-7 GPIO Circuit H_B_IO0 H_B_IO1 H_A_IO0 H_B_IO2 H_B_IO3 H_A_IO2 H_A_IO1 H_B_IO5 H_B_IO4 H_A_IO4 H_A_IO3 H_B_IO6 H_A_IO5 H_B_IO7 H_A_IO6 VCC3P3 VCC5P0 H_B_IO8 H_A_IO7 H_B_IO9 H_A_IO8 H_B_IO10 H_B_IO11 H_A_IO10 H_A_IO9 H_B_IO12 H_A_IO12 H_A_IO11 H_B_IO14 H_B_IO13... -
Page 24: Pinout
3 Development Board Circuit 3.8 GPIO 3.8.3 Pinout Table 3-7 J5 GPIO Pinout Signal Name Pin No. Socket Pin No. BANK Description H_A_IO0 General I/O 1.8V H_A_IO2 General I/O 1.8V H_A_IO1 General I/O 1.8V H_A_IO4 General I/O 1.8V H_A_IO3 General I/O 1.8V H_A_IO6 General I/O... -
Page 25: Table 3-9 J2 Gpio Pinout
3 Development Board Circuit 3.8 GPIO Signal Name Pin No. Socket Pin No. BANK Description H_A_IO15 General I/O 3.3V H_A_IO18 General I/O 3.3V H_A_IO17 General I/O 3.3V H_A_IO20 General I/O 3.3V H_A_IO19 General I/O 3.3V H_A_IO22 General I/O 3.3V H_A_IO21 General I/O 3.3V H_A_IO24... -
Page 26: Lvds
3 Development Board Circuit 3.9 LVDS Signal Name Pin No. Socket Pin No. BANK Description H_B_IO8 General I/O 3.3V H_B_IO10 General I/O 3.3V H_B_IO9 General I/O 3.3V H_B_IO12 General I/O 3.3V H_B_IO11 General I/O 3.3V H_B_IO14 General I/O 3.3V H_B_IO13 General I/O 3.3V H_B_IO16... -
Page 27: Pinout
3 Development Board Circuit 3.9 LVDS 3.9.3 Pinout Table 3-11 J3 FPGA Pinout Signal Name Pin No. Socket Pin No. BANK Description F_LVDS_A1_P A Channel 1+ 3.3V F_LVDS_A1_N A Channel 1- 3.3V F_LVDS_A2_P A Channel 2+ 3.3V F_LVDS_A2_N A Channel 2– 3.3V F_LVDS_A3_P A Channel 3+... -
Page 28: Ethernet
3 Development Board Circuit 3.10 Ethernet Signal Name Pin No. Socket Pin No. BANK Description F_LVDS_B2_N B Channel 2– 3.3V F_LVDS_B3_P B Channel 3+ 3.3V F_LVDS_B3_N B Channel 3– 3.3V F_LVDS_B4_P B Channel 4+ 3.3V F_LVDS_B4_N B Channel 4– 3.3V F_LVDS_B5_P B Channel 5+ 3.3V... -
Page 29: Pinout
3 Development Board Circuit 3.10 Ethernet 3.10.3 Pinout Table 3-13 Ethernet1 Pinout Signal Name Pin No. BANK Description PHY_MDC PHY1 management interface clock 3.3V PHY_MDIO PHY1 management interface data 3.3V PHY1_GTCLK RGMII/MII transmitter clock 3.3V PHY1_TXD0 RGMII/MII transmitter data 3.3V PHY1_TXD1 RGMII/MII transmitter data 3.3V... - Page 30 3 Development Board Circuit 3.10 Ethernet Signal Name Pin No. BANK Description PHY2_TXD2 RGMII/MII transmitter data 3.3V PHY2_TXD3 RGMII/MII transmitter data 3.3V PHY2_TXEN RGMII/MII transmitting enable 3.3V PHY2_RXC RGMII/MII receive clock 3.3V PHY2_RXD0 RGMII/MII receive data 3.3V PHY2_RXD1 RGMII/MII receive data 3.3V PHY2_RXD2 RGMII/MII receive data...
-
Page 31: Considerations
1. Handle with care and pay attention to electrostatic protection. 2. When you program the external FLASH, please refer to the MODE value in UG290, Gowin FPGA Products Programming and Configuration User Guide. 3. When the LVDS differential signal is used as input, the built-in 100Ω... -
Page 32: Gowin Software
5 Gowin Software Gowin Software For the details, you can see SUG100, Gowin Software User Guide. DBUG405-1.0E 25(25)
Need help?
Do you have a question about the DK_START_GW2AR-LV18EQ144PC8I7 and is the answer not in the manual?
Questions and answers