Data Communication Interfaces; Pci Express; Sdio 3.0 - Ublox JODY-W1 Series System Integration Manual

2.4 Data communication interfaces

2.4.1

PCI express

The PCI express bus of JODY-W1 series modules support PCIe v3.0 connectivity at transfer rates up
to 2.5 Gbaud. PCIe differential clock and data pairs accommodate a controlled impedance bus. The
parameters needed for the track impedance calculation are shown in
Figure 8: Differential pair, generic-controlled, impedance parameters
To ensure the bus signal integrity and avoid EMI issues, PCIe data lines must follow the
recommendations stated in
Signal group Parameter
PCIe differential data Single Ended impedance, ��
Differential impedance, ��
Common mode impedance, ��
Impedance control, ��
PCB signal attenuation margin
Bus skew length mismatch on same differential pair
Bus skew length mismatch between differential pairs
Isolation to other pairs and PCB signals
Table 20: PCI express bus requirements
2.4.2

SDIO 3.0

The SDIO 3.0 bus can support a clock frequency up to 208 MHz and thus requires special care to
ensure that the signal integrity requirements are met and EMI issues are minimized. The signals
should be routed with a single ended impedance of 50 Ω.
It is recommended that all signals in the bus are routed with the same length. The total bus length
should be minimal, and signals should have appropriate grounding in the surrounding layers.
The layout of the SDIO bus should be completed so that crosstalk with other parts of the circuit is
kept to a minimum. This ensures that the isolation between the signals, clock, and surrounding
busses/traces is adequate.
UBX-16012621 - R18
C1-Public
Table 20.
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JODY-W1 series - System integration manual
Figure
Min.
60
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0
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5*W
8.
Typ. Max. Unit
Ω
100
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-
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