Ublox JODY-W1 Series System Integration Manual page 12

Function Pin name
LTE_COEX_TX
LTE_COEX_RX
Control
PCIE_EN
SD_DES
SD_VDD_SEL
WL_DEV_WAKE
WL_HOST_WAK
E
BT_DEV_WAKE
BT_HOST_WAKE
PCIE_PME#
PCIE_CLKREQ#
PCIE_PERST#
WL_EN
BT_EN
LPO_IN
Radio ANT0
ANT1
ANT2
Other NC
Table 3: JODY-W1 pinout grouped by function
☞
Logical pin states are the same for active mode and sleep mode.
⚠
Do not apply any voltage to the digital, control, and radio signal groups while in Not Powered mode
to avoid damaging the module.
1 Not supported in current firmware releases
UBX-16012621 - R18
C1-Public
Pin no. Power Type Signal name
13 VIO O UART TX
14 VIO I UART RX
6 VIO I Configuration pin
7 VIO I Configuration pin
8 VIO I Configuration pin
9 VIO I Wi-Fi device wake-
up signal input
10 VIO O Wi-Fi Host wake-up
signal output
11 VIO I Bluetooth device
wake-up signal
12 VIO O Bluetooth Host
wake-up signal
40 VIO_SD OD PCIe control signal
41 VIO_SD OD PCIe control signal
42 VIO_SD I PCIe control signal
58 VIO I/PD Wi-Fi power enable
59 VIO I/PD BT power enable
60 - I Sleep clock input
24 VBAT RF Antenna signal
29 VBAT RF Antenna signal
21 VBAT RF Antenna signal
26, 56, - - Reserved
57
System description
JODY-W1 series - System integration manual
Remarks
an I2S interface for Bluetooth
audio.
LTE coexistence UART
LTE coexistence UART
See Table 7 for bootstrap
configuration
See Table 7 for bootstrap
configuration
See Table 7 for bootstrap
configuration
Asserted: Wi-Fi device must
wake-up or remain awake
Deasserted: Wi-Fi device may
sleep when the sleep criteria
is met.
Asserted: Host device must
wake-up or remain awake
Deasserted: Host device may
sleep when the sleep criteria
is met
Asserted: Bluetooth device
must wake-up or remain
awake
Deasserted: Bluetooth device
may sleep when sleep criteria
are met.
Asserted: Host device must
wake-up or remain awake
Deasserted: Host device may
sleep when sleep criteria are
met
PCIe power management
event output
PCIe clock request signal
PCIe System reset
32.768 kHz clock input, fail
safe pin.
See also Module architecture
See also Module architecture
See also Module architecture
Do not connect
Active Power down
1 O Tristate
1 I Disabled
I Disabled
I Disabled
I Disabled
I Tristate
O Tristate
I Tristate
O Tristate
OD OD
OD OD
I Disable
I/PD I/PD
I/PD I/PD
I I
RF RF
RF RF
RF RF
NC NC
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