Supply Interfaces; Module Supply Design - Ublox JODY-W1 Series System Integration Manual

• It is highly recommended to strictly follow the specific guidelines provided by the antenna
manufacturer regarding correct installation and deployment of the antenna system, including
PCB layout and matching circuitry.
• Further to the custom PCB and product restrictions, antennas may require tuning/matching to
reach the target performance. It is recommended to plan measurement and validation activities
with the antenna manufacturer before releasing the end-product to manufacturing.
• The receiver section may be affected by noise sources like hi-speed digital busses. Avoid placing
the antenna close to busses as DDR or consider taking specific countermeasures like metal
shields or ferrite sheets to reduce the interference.
• Take care of interaction between co-located RF systems like LTE sidebands on 2.4 GHz band.
Transmitted power may interact or disturb the performance of JODY-W1 modules where specific
LTE filter is not included.

2.3 Supply interfaces

2.3.1

Module supply design

Though the GND pins are internally connected, it is recommended to connect all the available ground
pins to solid ground on the application board as a good (low impedance) connection to external ground
can minimize power loss and improve RF and thermal performance. JODY-W1 modules must be
sourced through VBAT and VIO/VIO_SD pins with proper DC power supplies that comply with the
requirements summarized in
Good connection of the JODY-W1 series module power supply pins with DC supply source is required
for accurate RF performance and schematic guidelines are summarized below:
• All power supply pins must be connected to an appropriate DC source.
• Any series component with Equivalent Series Resistance (ESR) greater than a few mΩ should be
avoided. Only exceptions to this rule are ferrite beads used for DC filtering, however those parts
should be used carefully to avoid instability of the DC/DC supply powering the module and are in
general not required.
• A minimum bulk capacitance of 10 µF on VBAT rail is required close to the module to help filter
current spikes from the RF section. The preferred choice is a ceramic capacitor with X7R or X5R
dielectric due to low ESR/ESL. Special care should be taken in the selection of X5R/X7R dielectrics
due to capacitance derating vs DC bias voltage.
• Additional bypass capacitors in the range of 100 nF to 1 µF on all supply pins are required for high
frequency filtering. The preferred choice is a ceramic capacitor with X7R or X5R dielectric due to
low ESR/ESL. Smaller size bypass capacitors should be chosen for the manufacturing process to
minimize ESL.
UBX-16012621 - R18
C1-Public
Table 4.
Design-in
JODY-W1 series - System integration manual
Page 27 of 72