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Function Pin name
Power
VBAT
VIO
VIO_SD
GND
Exposed Pins
Digital
SD_CLK
SD_CMD
SD_D0
SD_D1
SD_D2
SD_D3
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_RDN
PCIE_RDP
PCIE_TDN
PCIE_TDP
BT_UART_TX
BT_UART_RX
BT_UART_RTS
BT_UART_CTS
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
I2S_CLK
I2S_WS
I2S_DI
I2S_DO
UBX-16012621 - R18
C1-Public
Pin no.
Power
Type Signal name
2
VBAT
PWR
Module supply input Voltage supply range: 3.2 V –
3
VIO
PWR
VIO supply
4
VIO_SD PWR
VIO supply for SDIO
1, 5, 19,
GND
GND
20, 22,
23, 25,
27, 28,
30, 31,
49
-
GND
GND
53
VIO_SD I
SDIO Clock
52
VIO_SD I/O
SDIO Command
54
VIO_SD I/O
SDIO data 0
55
VIO_SD I/O
SDIO data 1
50
VIO_SD I/O
SDIO data 2
51
VIO_SD I/O
SDIO data 3
43
-
I
PCIe 100 MHz clock
differential input
44
-
I
45
-
I
PCIe receiver
differential input
46
-
I
47
-
O
PCIe transmitter
differential output
48
-
O
36
VIO
O
UART TX
37
VIO
I
UART RX
38
VIO
O
UART RTS
39
VIO
I
UART CTS
16
VIO
I/O
PCM clock
15
VIO
I/O
PCM Frame Sync
18
VIO
I
PCM data in
17
VIO
O
PCM data out
34
VIO
I/O
I2S clock
35
VIO
I/O
I2S Word Sel.
32
VIO
I
I2S data in
33
VIO
O
I2S data out
System description
JODY-W1 series - System integration manual
Remarks
4.8 V
Nominal supply range: 1.8 V
or 3.3 V
Nominal supply range: 1.8 V
or 3.3 V.
Also used for PCIe out-of-
band signals.
Connect to Ground
SDIO Clock input
SDIO command line
SDIO data line bit [0]
SDIO data line bit [1]
SDIO data line bit [2]
SDIO data line bit [3]
AC coupling capacitors 100
pF included in the module
DC coupled inputs. Place 100
nF AC coupling capacitors
close to the host TDN/TDP
differential output.
AC coupling capacitors100 nF
included in the module.
Connect to the host RDN/RDP
differential input directly.
BT UART, connect to Host RX O
BT UART, connect to Host TX I
BT UART, connect to Host
CTSn
BT UART, connect to Host
RTSn
Input if slave, Output if
master
Alternate function: I2S clock
Input if slave, Output if
master
Alternate function: I2S Word
Select
Alternate function: I2S data in I
Alternate function: I2S data
out
Reserved for additional I2S
interface. Do not connect.
The I2S interface shares the
pins with the PCM interface.
Use the PCM pins to connect
Active Power down
VBAT
VBAT
VIO
VIO
VIO_SD VIO_SD
GND
GND
GND
GND
I
Tristate
I/O
Tristate
I/O
Tristate
I/O
Tristate
I/O
Tristate
I/O
Tristate
I
Disabled
I
Disabled
I
Disabled
I
Disabled
O
Tristate
O
Tristate
Tristate
Tristate
O
Tristate
I
Tristate
I/O
Tristate
I/O
Tristate
Tristate
O
Tristate
I/O
Tristate
I/O
Tristate
I
Tristate
O
Tristate
Page 11 of 72
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