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■ BLOCK DIAGRAM
DCLK
DSIO
DST2
System clock
Clock generator
(CLG)
IOSC
FOUT0–1
oscillator
OSC1
OSC1
oscillator
OSC2
OSC3
OSC3
oscillator
OSC4
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
#RESET
(POR)
V
DD
Power generator
V
SS
(PWG)
V
D1
CPU core & debugger
(S1C17)
Interrupt request
16-bit internal bus
Interrupt signal
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
Supply voltage
detector
(SVD3)
16-bit timer
(T16)
5 Ch.
16-bit PWM timer
(T16B)
1 Ch.
Seiko Epson Corporation
Multiplier/divider
Coprocessor bus
(COPRO2)
Internal RAM
32-bit RAM bus
4K bytes
Flash memory
Instruction bus
64K bytes
P00–07
P10–13
P20–27
P30–37
PD0–D1
PD3–D4
PD2
RTC1S
EXSVD0
TOUT00–01
CAP00–01
EXCL00–01
S1C17M10
Flash
programming
V
PP
voltage booster
UART
USIN0
(UART2)
USOUT0
1 Ch.
Synchronous
SDI0
serial interface
SDO0
(SPIA)
SPICLK0
1 Ch.
#SPISS0
I
2
C
SDA0
(I2C)
SCL0
1 Ch.
Smart card
interface
SMCCLK0
(SMCIF)
SMCIO0
1 Ch.
V
C1–5
C
P1–5
COM0–7
LCD driver
COM8–16/
(LCD16A)
SEG87–80
SEG0–79
LFRO
Display RAM
352 bytes
3
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