SOLTEK SL-67D Manual page 39

CPU to PCI Write When this field is Enabled, writes
from the CPU to the PCI bus are
Buffer
buffered, to compensate for the
speed differences between the CPU
and the PCI bus. When Disabled,
the writes are not buffered and the
CPU must wait until the write is
complete before starting another
write cycle.
The choice: Enabled, Disabled.
PCI Dynamic When Enabled, every write
Bursting transaction goes to the write buffer.
Burstable transactions then burst on
the PCI bus and nonburstable
transactions donit.
The choice: Enabled, Disabled.
PCI Master 0 WS When Enabled, writes to the PCI
Write bus are executed with zero wait
states.
The choice: Enabled, Disabled
PCI Delay The chipset has an embedded 32-bit
Transaction posted write buffer to support delay
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
The choice: Enabled, Disabled.
PCI #2 Access #1 When PCI#2 (AGP bus) access to
Retry PCI#1 (PCI bus) has a error
occurred.
The choice: Enabled, Disabled.
AGP Master 1 WS When Enabled, writes to the
Write AGP(Accelerated Graphics Port) are
executed with one wait states.
The choice: Enabled, Disabled.
Award BIOS Setup 35