Operating The Adpa1105-Evalz With The Drain Bias Pulser Board - Analog Devices ADPA1105-EVALZ User Manual

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ADPA1105-EVALZ

OPERATING THE ADPA1105-EVALZ WITH THE DRAIN BIAS PULSER BOARD

The ADPA1105-EVALZ ships with a drain bias pulser board. A
block diagram of the pulser board is shown in Figure 4. The pulser
board has two primary components. The BSC340N08NS3 is an
80 V/23 A, metal-oxide semiconductor field effect transistor
(MOSFET) that switches the drain voltage to the ADPA1105
on and off, and the
LTC7000
metal-oxide semiconductor (NMOS), static switch driver that
controls the MOSFET.
The pulser board plugs into the P3 and P4 headers of
ADPA1105-EVALZ and can be configured to provide a pulsed
drain voltage and a negative gate control voltage to control the
biasing of the ADPA1105.
3300µF
INPUTS
FROM USER
J1
2
1
VDD
VDD
4
3
6
5
8
7
10
9
VGG1, VGG2
VGG1, VGG2
12
11
14
13
16
15
GND
18
17
GND
PULSE
PULSE
20
19
22
21
24
23
V
/
DET_BIAS
26
25
V
REF_BIAS
User Guide
is a high-side, negative channel
23
24
VDD
C10
C11
C3
C2
+
+
1000µF
180pF
0.1µF
80V
80V
100V
100V
R5
0Ω
LTC7000EMSE-13PBF
1
V
C13
R1
1µF
3
100kΩ
V
5
V
6
FAULT
7
TIMER
8
INP
PULSE
C12
0.001µF
CMPD3003
VGG1, VGG2
2
4
6
8
1
3
5
7
Figure 4. Analog Devices, Inc., Pulser Board Schematic
Table 3. Pulser Board J1, J2, and J3 Header Connections
to ADPA1105
Header
Header Pin Number
J1
1, 2, 3, 4, 5, 6
7, 8, 25
9, 10, 11, 12, 13, 14
15, 16, 17, 18, 21, 22, 23, 24
19, 20
26
J2
1, 3, 5, 7, 9, 10, 11, 12, 13, 14, 15,
17, 19, 21, 22, 23, 24
2, 16, 18, 20
4, 6, 8
J3
1, 2, 3, 4, 5, 7, 9, 11, 12, 13, 14,
15, 16, 17, 19, 21, 23
6, 8 ,10
24
21
19
17
15
13
11
9
7
5
3
22
20
18
16
14
12
10
8
6
4
PULSED_VDD_DUT
C4
C7
C8
C9
10µF
10µF
10µF
10µF
100V
100V
100V
100V
16
U1
+
SNS
IN
14
SNS
CC
12
BST
CCUV
11
TS
10
TGUP
9
TGDN
PAD
U2
V
DET_BIAS
V
REF_BIAS
10
12
14
16
18
20
22
24
CONNECTS DIRECTLY TO
J3
EVAL BOARD P4
9
11
13
15
17
19
21
23
Rev. 0 | Page 7 of 13
1
CONNECTS DIRECTLY
J2
TO EVAL BOARD P3
2
P1
PEC02SAAN
C1
0.1µF
PULSED_VDD
1
2
R7
3
1kΩ
R8
4
0Ω
R3
1kΩ
/
UG-1674
Header Pin Name
VDD
No connect
VGG1, VGG2
GND
PULSE
V
, V
DET_BIAS
REF_BIAS
GND
No connect
PULSED_VDD_DUT
GND
VGG1, VGG2
V
, V
DET_BIAS
REF_BIAS
S
8
Q1
7
6
5
G
D
BSC340N08NS3
J4
PULSED_VDD
FOR MONITORING
WITH HIGH-Z
OSCILLOSCOPE PROBE

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