Lexmark C752 Technical Reference page 324

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Standard Protocol Data Transfer Sequence
The following illustration shows the typical data transfer sequence on the parallel
interface. See Table 8-2 for typical parallel interface timings on the parallel interface.
Controls data flow control with BUSY and ACKNLG* signals. Does not carry
out data transfer by ignoring the BUSY or ACKNLG* signal. (The system can
carry out data transfer to the printer only when the level of the BUSY signal is
low and after confirming the ACKNLG* signal is high.)
Uses standard transistor-transistor logic (TTL) levels for all interface control
signals and input data. Interface conditions are based on TTL levels. All
printer outputs are totem-pole TTL devices. All printer input/output (I/O) are
devices with an internal pull-up resistor to 5 V. Rise and fall times of each
signal must be less than 1,500 nanoseconds (ns) without slope reversal.
DATA1-8
STROBE*
BUSY
ACK*
8-15
A B C
D
Interfaces
G
F
E