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UM11666
SC18IS606-EVB evaluation board
Rev. 1.0 — 28 September 2021
Document information
Information
Content
Keywords
SC18IS606, I
SPI bridge
Abstract
SC18IS606 is designed to serve as an interface between a standard I
bus of a microcontroller and an SPI bus. This allows the microcontroller
to communicate directly with SPI devices through its I
operates as an I
2
C to SPI, SC18IS602, SPI Controller, SPI master, I
2
C target and an SPI master.
User manual
2
C bridge,
2
C-
2
C-bus. SC18IS606
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Table of Contents
Related Manuals for NXP Semiconductors SC18IS606-EVB
Summary of Contents for NXP Semiconductors SC18IS606-EVB
- Page 1 UM11666 SC18IS606-EVB evaluation board Rev. 1.0 — 28 September 2021 User manual Document information Information Content Keywords SC18IS606, I C to SPI, SC18IS602, SPI Controller, SPI master, I C bridge, SPI bridge Abstract SC18IS606 is designed to serve as an interface between a standard I bus of a microcontroller and an SPI bus.
- Page 2 UM11666 NXP Semiconductors SC18IS606-EVB evaluation board Revision history Date Description v.1.0 20210928 Initial version UM11666 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. User manual Rev. 1.0 — 28 September 2021...
- Page 3 UM11666 NXP Semiconductors SC18IS606-EVB evaluation board Important notice NXP provides the enclosed product(s) under the following conditions: This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals.
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Page 4: Introduction
C controller can write, read, and program the serial EEPROM without requiring an SPI slave to be connected to the board. The 3V3 power for the SC18IS606-EVB evaluation board should be supplied via this I interface header as well. The SC18IS606-EVB evaluation board also has an SPI interface header (JP1) to allow other SPI slave devices to be connected to the evaluation board. -
Page 5: Headers And Jumpers
UM11666 NXP Semiconductors SC18IS606-EVB evaluation board 4.1 Headers and jumpers Please refer to Figure 1 to find the location of connectors and jumpers on the SC18IS606-EVB evaluation board. Figure 1. Headers and jumpers 4.2 Jumper settings Table 1. Jumper settings Header Jumper on... -
Page 6: Schematic, Board Layout And Bill Of Materials
0x55 0x56 0x57 4.3 Schematic, board layout and bill of materials The schematic, board layout and bill of materials for the SC18IS606-EVB evaluation board are available at http://www.nxp.com/SC18IS606-EVB. 4.4 Sample control sequences from I C controller 4.4.1 GPIO as input... -
Page 7: Spi Mode And Clock Configuration
UM11666 NXP Semiconductors SC18IS606-EVB evaluation board 4.4.3 SPI mode and clock configuration Write 0x50 0xF0 0x02 // Set SPI mode 0, MSB first, SPI clock to 115KHz Write 0x50 0xF0 0x05 // Set SPI mode 1, MSB first, SPI clock to 461KHz 4.4.4 Device ID read... -
Page 8: Legal Information
6.1 Definitions and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this Draft —... - Page 9 UM11666 NXP Semiconductors SC18IS606-EVB evaluation board Tables Tab. 1. Jumper settings ..........5 Tab. 4. JP3 – SC18IS606 I2C target address ....6 Tab. 2. JP1 - SPI header ..........5 Tab. 5. Errata list ............7 Tab. 3. JP2 - I2C ............6 Figures Fig.
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Page 10: Table Of Contents
UM11666 NXP Semiconductors SC18IS606-EVB evaluation board Contents Introduction ............4 Finding kit resources and information on the NXP web site ..........4 Collaborate in the NXP community ....4 Getting ready ............4 Kit contents ............4 Getting to know the hardware ......4 Headers and jumpers ........
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