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NXP Semiconductors
Developer's Guide
MCU VIZNAS Solution Developer's Guide
TABLE OF CONTENTS
1
INTRODUCTION ............................................................................................................................................ 5
1.1
RT106F VISION CROSSOVER PROCESSOR OVERVIEW ...................................................................................... 5
2
GETTING TO KNOW THE SLN-VIZNAS-IOT ..................................................................................................... 7
2.1
2.2
2.3
2.4
2.4.1
Application Chain of Trust .................................................................................................................... 10
2.4.2
Flash Image Configuration Area (FICA) and Image Verification .......................................................... 11
2.4.3
Image Certificate Authority (CA) and Application Certificates ............................................................. 11
3
GET STARTED WITH MCUXPRESSO TOOL SUITE .......................................................................................... 13
3.1
IDE ............................................................................................................................................. 13
3.2
SDK ............................................................................................................................................... 14
3.3
I
3.4
4
BUILDING AND PROGRAMMING ................................................................................................................. 21
4.1
4.2
5
BOOTLOADER ............................................................................................................................................. 26
5.1
............................................................................................................................................ 26
5.2
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5.2.1
Transfers .............................................................................................................................................. 27
5.2.2
Testing OTA/OTW Updates .................................................................................................................. 28
5.3
5.4
6
AUTOMATED MANUFACTURING TOOLS ..................................................................................................... 33
6.1
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SLN-VIZNAS-IOT Developer's Guide, Rev. 1.2, 11/2020
1
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Document Number: SLN-VIZNAS-IOT-DG
Rev 1.2, 11/2020
........................................................................................ 27
NXP Semiconductors
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Related Manuals for NXP Semiconductors SLN-VIZNAS-IOT
Summary of Contents for NXP Semiconductors SLN-VIZNAS-IOT
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Page 1: Table Of Contents
Document Number: SLN-VIZNAS-IOT-DG Developer’s Guide Rev 1.2, 11/2020 MCU VIZNAS Solution Developer’s Guide TABLE OF CONTENTS INTRODUCTION ............................5 RT106F VISION CROSSOVER PROCESSOR OVERVIEW ..................5 GETTING TO KNOW THE SLN-VIZNAS-IOT ..................... 7 ............................7 ARDWARE VERVIEW ............................8 OFTWARE VERVIEW ............................ - Page 2 21: “P ” O ............................19 IGURE ROPERTIES PTION 22: P ............................20 IGURE ROPERTIES INDOW 23: P ......................21 IGURE ROJECT XPLORER IGHLIGHT ROJECT 24: B ..............................21 IGURE UILD ROJECT SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors...
- Page 3 " ........................47 IGURE SING CUST PROG ............................ 48 IGURE FILE FORMAT SAGE TABLE OF TABLES 1: S ......................... 6 ABLE UPPORTED OMPUTER ONFIGURATIONS 2: W & P ........................... 6 ABLE REQUENCY OWER SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors...
- Page 4 3: R ............................49 ABLE EFERENCE OCUMENTS 4: A .......................... 49 ABLE BBREVIATIONS AND EFINITIONS 5: R ............................... 50 ABLE EVISION ISTORY SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors...
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Page 5: Introduction
1 Introduction NXP’s MCU-based SLN-VIZNAS-IOT development kit provides OEMs with a fully integrated, self-contained, software and hardware solution. This includes the i.MX RT106F run-time library and pre-integrated machine learning face recognition algorithms, as well as all required drivers for peripherals, such as camera and memories. - Page 6 EUROPEAN DECLARATION OF CONFORMITY (Simplified DoC per Article 10.9 of the Radio Equipment Directive 2014/53/EU) This apparatus, namely SLN-VIZNAS-IOT, conforms to the Radio Equipment Directive 2014/53/EU. The full EU Declaration of Conformity for this apparatus can be found at this location: https://www.nxp.com/...
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Page 7: Getting To Know The Sln-Viznas-Iot
2 Getting to Know the SLN-VIZNAS-IOT 2.1 Hardware Overview The SLN-VIZNAS-IOT kit is intended to provide a reference for a real product design. The kit is designed using a small form factor which takes into account many of the design considerations a hardware engineer would make when creating a product. -
Page 8: Software Overview
Figure 3: VIZNAS HW Block Diagram 2.2 Software Overview The SLN-VIZNAS-IOT kit has been built and designed in such a way that enables best security practices while keeping a development kit feel. The main security mechanism that has been implemented is a series of image verification stages that are required for every image programmed onto the device. -
Page 9: Device Memory Map
0x61D80000 Btld SIGN CERT 0x61FC0000 0x61FC0000 FICA Table: FICA Table: DESCRIPTOR DESCRIPTOR AppType, BootType, ComBits AppType, BootType, ComBits RECORDS (x3) RECORDS (x3) ImgType, AppAddr ImgType, AppAddr Signatures Figure 5: Device Memory Map SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 10: Security Architecture
The CA is used to create signing entities for the bootloader and application. A certificate from the CA is stored in the SLN-VIZNAS-IOT’s filesystem and is used to verify the signatures of the signing entity certificates. In addition, locally stored certificates from the signing entities are used to verify the signature of firmware images coming in over the OTA/OTW bootloader interface. -
Page 11: Flash Image Configuration Area (Fica) And Image Verification
These bypasses should not be deployed in production. Again, the default configuration of the SLN-VIZNAS-IOT is to have HAB disabled and signature verifications bypassed. This is to ensure a smooth development experience. - Page 12 0x61CC0000 in the filesystem. For more detail, see Figure 5: Device Memory Map. These certificates are used when Image Verification (see section Enabling Image Verification) is enabled to validate the signature provided when performing a secure update. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors...
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Page 13: Get Started With Mcuxpresso Tool Suite
Its debug connections support every NXP evaluation boards with industry-leading open-source and commercial debug probes from ARM®, P&E Micro® and SEGGER®. NOTE: The SLN-VIZNAS-IOT requires MCUXpresso IDE version 11.2.1 or greater. 1. To download NXP MCUXpresso IDE for free go online to: www.nxp.com/MCUXpresso 2. -
Page 14: Install The Sdk
It is available in custom downloads based on user selections of MCU, evaluation board, and optional software components. Before building the SLN-VIZNAS-IOT SDK example projects, the target SDK needs to be imported into MCUXpresso IDE. The MCUXpresso SDK for the SLN-VIZNAS-IOT can be downloaded from NXP’s by clicking Select Development Board and searching for “SLN-VIZNAS-IOT”... -
Page 15: Figure 11: Select All Sdk Components
After updating the operating system, be sure to click Select All to make sure all required components get added. Figure 11: Select all SDK components With these options selected, press the Download SDK button at the bottom of the page. Figure 12: Download SDK SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 16: Figure 13: Drag And Drop Sdk
For each package, a confirmation window will pop-up. Select OK to validate. Figure 14: Import SDK Confirmation Window Once the package has been imported, it will be displayed in the Installed SDKs window in MCUXpresso. Figure 15: SDK Import Successful SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 17: Mport Asln-Viznas-Iot Project
3.3 Import a SLN-VIZNAS-IOT Project The SLN-VIZNAS-IOT SDK allows you to import existing application examples as a development starting point. The following steps will show you how to import one of these example projects into MCUXpresso IDE. From the Quickstart Panel, select Import SDK example(s). -
Page 18: Figure 18: Import Examples
Once the projects have successfully been imported, they will be listed in the project explorer ready to be built and run. Figure 19: Projects Successfully Imported SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 19: Optional) Increase Clock Drive Strength
To configure this preprocessor macro, right click on the sln_viznas_iot_elock_oobe project in the Project Explorer pane as shown in the figure below and select Properties, found near the bottom of the context menu: Figure 20: Right-Click Project Figure 21: “Properties” Option SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 20: Figure 22: Properties Window
4. Change the value from 1 to 0 and click OK. Repeat the previous steps for the CAMERA_DRIVE_STRENGTH_LOW preprocessor macro found under MCU C COMPILER -> Preprocessor, then003A 5. Click Apply and Close. Figure 22: Properties Window SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 21: Building And Programming
The E-Lock OoBE is the out-of-box application used to demonstrate the capabilities of the Oasis Lite machine learning engine for secure face recognition. This is the application (in addition to the bootloader and bootstrap) that is flashed on your SLN-VIZNAS-IOT kit by default. -
Page 22: Figure 25: Console 'Build' Output
Figure 26: .axf to .bin .bin files are useful for flashing with OTW/OTA, MSD, and the automated manufacturing tools. Each of these features are described in greater detail later in the guide. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 23: Flash And Debug Sln-Viznas-Iot Project
With the elock_oobe project compiled, it is now time to program its associated binary into flash. Flashing the SLN-VIZNAS-IOT kit will require a Segger J-Link with a 9-pin Cortex-M Adapter and V6.62a or newer of the J-Link Software and Documentation Pack found on the Segger website at: https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack. -
Page 24: Figure 29: Quickstart Panel - D
Debug will only flash and debug the project currently highlighted in the Project Explorer panel. Figure 29: Quickstart Panel - Debug Select the J-Link probe that is connected to your kit and press OK. Figure 30: Probe Discovery Window SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 25: Figure 31: Flash Download Inp
Finally, press the Run button found in the toolbar to begin running the application. Figure 33: Debug Toolbar - Run Button To learn more about debugging in MCUXpresso, check out the MCUXpresso IDE User Guide. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 26: Bootloader
Once the boot flow reaches the bootloader, the bootloader must decide what to do. The below shows the three options available to the bootloader. The subsequent sections describe the OTA/OTW and USB MSD modes. Figure 34: Bootloader Flow SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 27: Over-The-Air (Ota)/Over-The-Wire (Otw) Updates
4-byte size field and a JSON message. This allows the OTA/OTW data interface to be compatible across a wide range of interfaces. Figure 35: Transfer Format Each transfer is followed by a transfer response. Figure 36: Request/Response Flow SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 28: Testing Ota/Otw Updates
This section will describe the setup steps necessary to perform an OTA update. To perform an OTA update using the test script, the SLN-VIZNAS-IOT will need to be connected to a Wi-Fi network and the proper bit in the FICA table will need to be set to indicate to the bootloader that an OTA update is being expected. -
Page 29: Figure 37: Serial Header Connections
Once all args are specified, the script will produce output like the following: ~/bootloader_4343W/unit_tests $: python3 fwupdate_client.py viznas OTA B PATH-TO- BIN/sln_viznas_iot_elock_oobe_bankB_debug.bin None Device IP:192.168.0.166 unit_test_fwupdate_send_ota_command {"messageType": 2} unit_test_fwupdate_start_req Sending Start Request SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 30: Mass Storage Device (Msd) Update
{"messageType": 1, "fwupdate_message": {"messageType": 1, "fwupdate_server_message": {"messageType": 2}}} Figure 39: "fwupdate_client.py" w/ Args Upon completion, the SLN-VIZNAS-IOT will automatically restart itself and switch over to the new application bank, running the new application that was just flashed. 5.3 Mass Storage Device (MSD) Update The bootloader application supports firmware update over USB Mass Storage Device (MSD). -
Page 31: Figure 41: Msd Mode Lights
“good” binary in case a corrupted image gets flashed due to a crash during the flashing process. Figure 43: Dragging-and-Dropping New Binary The new binary will be copied onto your SLN-VIZNAS-IOT, and the kit will automatically restart once flashing is complete. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020... -
Page 32: Generate Bankb Binary
Rebuild your application using the steps found under Building and Programming, making sure to generate a binary from the .axf. The generated binary will be able to reflash the main application when the kit is running from Application Bank A. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 33: Automated Manufacturing Tools
The Ivaldi tools can be downloaded under Software and Tools on the official webpage for the SLN-VIZNAS-IOT. Extract the ZIP file and open the README.md to start using the tool. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 34: Creating A Signing Entity
6.3 Creating a Signing Entity The basis of the security architecture implemented in the SLN-VIZNAS-IOT is signed application images. Signing requires the use of a Certificate Authority (CA). NXP has its own CA for signing applications at the factory, but the root CA is not something that is shared with customers. -
Page 35: Move Boot Jumper
Scripts/ota_signing folder for more details about the directory structure and files that were generated by the script. 6.4 Move Boot Jumper Running the flashing scripts, the SLN-VIZNAS-IOT boot jumper (J27) will need to be moved from position “1” to position “0”. Figure 49: SLN-VIZNAS-IOT Boot Jumper... -
Page 36: Open Boot Programming
6.5 Open Boot Programming The SLN-VIZNAS-IOT can be programmed with or without security features enabled. The steps to enable secure booting of the kit can be found in later sections. This section will describe the steps necessary to program the board without security features enabled. -
Page 37: Optional) Enabling Encrypted Execute-In-Place (Exip) And High Assurance Boot (Hab)
HAB and eXIP. By the end of this section, the bootstrap will be signed to work with the HAB and the bootloader and the elock_oobe will be encrypted with individual encrypted context. The bootloader and elock_oobe have SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 38: Preparing The Environment
CA and application certificate that will be loaded into the flash. It will also be used to generate the FICA table used to validate the application signature. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 39: Figure 53: Setup
SUCCESS: Generated boot directive file. Generating secure boot(.sb) file to enable HAB... SUCCESS: Created secure boot file to enable HAB. Cryptographically signing flashloader image ... SUCCESS: Created signed flashloader image. Figure 53: setup_hab.py Script SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 40: Optional) Enabling Encrypted Execute In Place (Exip)
SUCCESS: Device is ready for blhost! Reading device unique ID... get-property SUCCESS: Device serial number is Rin4ZdJBFg4= Programming efuse CFG5... efuse-program-once SUCCESS: Programmed efuse CFG5. Programming efuse CFG4... efuse-program-once SUCCESS: Programmed efuse CFG4. Resetting device... reset SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 41: Enabling High Assurance Boot (Hab)
SUCCESS: Device serial number is Rin4ZdJJIhA= Writing memory config option block... fill-memory SUCCESS: Config option block loaded into RAM. Configuring FlexSPI... configure-memory SUCCESS: FlexSPI configured. Erasing flash... flash-erase-region SUCCESS: Flash erased. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 42: Preparing Bootstrap, Bootloader, And Main Application Images
MCUXpresso workspace as shown in the following figure. If these projects are not in your MCUXpresso workspace, follow the steps in the Import a SLN-VIZNAS-IOT Project section. Figure 57: Importing the Applications for HAB and eXIP Before creating the images, a modification needs to be made to the bootstrap. -
Page 43: Figure 58: Unsetting The Xip Boot
Create S-Record generates a “.s19” file, while our script requires “.srec” files. Simply right click on the s19 file generated in the previous step and rename it with the “.srec” file extension type. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 44: Generating Secure Binary
It’s important to know that the file names that are in this file are the names the script will look for. If the files in your Image_Binaries folder differ, please change the names of the SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 45: Preparing For Programming The Device
• ca_crt.bin – This is the public image CA certificate • fica_table.bin – This is the Flash Image Configuration Area generated when creating a signed bootloader and elock_oobe. At this point, your Image_Binaries folder should look similar to the following: SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 46: Enabling And Programming The Signed And Encrypted Binaries
The following figure shows example output for the command if run with eXIP enabled: (env) ivaldi_sln_viznas_iot/Scripts/sln_viznas_iot_secure_boot/manf $ python3 prog_sec_app.py -c my_test_ca Establishing connection... SUCCESS: Communication established with device. Loading flashloader... SUCCESS: Flashloader loaded successfully. Jumping to flashloader entry point... SUCCESS: Device jumped to execute flashloader. SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 47: Figure 65: Using " Cust
If done correctly, the device will reset itself. One complete, the board will need to be unplugged and the boot jumper (J27) will need to be returned to its default “1” position. PLEASE NOTE, THE LOCK_DEVICE.PY SHOULD ONLY BE USED IN PRODUCTION AS THIS DISABLES DEBUGGER ACCESS SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 48: Filesystem
7 Filesystem The SLN-VIZNAS-IOT has implemented a custom file system to manage files on-chip. A custom file system is used because: The device executes code from flash (XiP) which means it needs to read flash from RAM functions. HyperFlash has 256 KB sector sizes which do not allow for the granularity of files. -
Page 49: Document Details
System Mass Storage Device Original Equipment Manufacturer Over the Wire One Time Programmable Read Only Memory Real-Time Operating RTOS System Software Development Kit Universal asynchronous UART receiver-transmitter Table 4: Abbreviations and Definitions SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... -
Page 50: Revision History
Section Cooper 11/4/20 Production 1.2 and fix to the Open Carnahan Boot Programming section Cooper 10/28/20 Production 1.1 Minor Corrections Carnahan Cooper 10/13/20 Production 1.0 Initial Version Carnahan Table 5: Revision History SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors... - Page 51 Arm7, Arm9, Arm11, SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors big.LITTLE, CoreLink, CoreSight, DesignStart, Mali, Mbed, NEON, POP, Sensinode, Socrates, ULINK and Versatile are trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights...
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