System Emif Access Slave Interface (Ses); System Msmc Sram Access Slave Interface (Sms); System Master Interface; External Memory Master Interface - Texas Instruments MSMC User Manual

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2.1.2.1 System EMIF Access Slave Interface (SES)

2.1.2.2 System MSMC SRAM Access Slave Interface (SMS)

2.1.3 System Master Interface

2.1.4 External Memory Master Interface

SPRUGW7—November 2010
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The SES interface handles accesses to external DDR3 memory and memory-mapped
registers inside the EMIF module that originate from a system master that is not a C66x
CorePac. Accesses presented on this interface to any addresses outside of the address
range mapped to the external memory or the EMIF memory mapped registers result in
an addressing error returned to the requesting master. The address width on this
interface is 32 bits; address extension to a 36-bit external memory address is done
inside the MSMC as described in
(MPAX)'' on page 2-4.
The SMS interface handles accesses to MSMC SRAM that originate from a system
master that is not a C66x CorePac. Accesses from masters in the system to MSMC
configuration registers are also expected to be presented at this interface. Any accesses
from the SMS interface that do not address the MSMC SRAM or configuration
registers result in an addressing error returned to the requesting master.
The MSMC features one master interface for the C66x CorePac to access system
resources other than the MSMC SRAM, MSMC MMRs, DDR3 memory, and the EMIF
MMRs. Traffic from the system slave interfaces does not pass through the master
interface.
The external memory interface (EMIF) module is connected to the MSMC through the
external memory master interface. The address width for this interface is 36 bits
because supports the extended memory addressing space beyond 4 GB. The MSMC
implements an address extension to 36 bits as described in
Address Extension (MPAX)''
KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide
''Memory Protection and Address Extension
on page 2-4.
2.1 Functional Overview
Chapter 2—MSMC Architecture
''Memory Protection and
2-3