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3.1 Clock Connection
The EVM allows for an external differential clock, an external single-ended clock, or a clock signal from
the TSWDC155EVM controller card. Jumper J11 selects either the external clock or a clock from the
TSWDC155EVM. J5 grounds the negative clock if a single-ended clock is applied.
connection circuit.
SBAU409 – SEPTEMBER 2022
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J1
EXT_SMPL_CLKP
1
R4
DNP
49.9
GND
EXT_SMPL_CLKM
J5
J2
1
1
2
GND
GND
EXT_SMPL_CLKP
1
SMPL_CLKP
2
FPGA_SMPL_CLKP
3
J11
Figure 3-2. Clock Connection
Copyright © 2022 Texas Instruments Incorporated
Digital Interface
Figure 3-2
shows the clock
ADS9218EVM-PDK Evaluation Module
9
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