Advertisement
SYSTEM DESCRIPTION, INSTALLATION, AND MAINTENANCE MANUAL
MCS--4200/7200 Multi--Channel SATCOM System
2
The POST sequence of tests does not terminate when an out-of-tolerance
condition is encountered. Instead, the sequence continues to complete as
many tests as possible to record all available information regarding existing
failures. An individual LRU that successfully passes POST is declared to be
fully functional. POST must take into account failures detected by
continuous monitoring (i.e., if POST passes, but testing unique to
continuous monitoring has detected and logged a current failure, then the
POST result is logged as a failure).
3
After executing its own POST, the SDU commands a system-wide functional
test of the HPA(s), HSU and ACU/BSU(s) (including the HGAs, HGA
diplexer/LNA, and HPR) as applicable for the installed equipment in
accordance with the system configuration pins (see MECHANICAL
INSTALLATION). The SDU then processes the results of the functional tests
from these LRUs. The SDU commands the functional test as follows
through:
• BIT request in the HSU command word
• SSM field of the HPA command word(s) for the HPA
• SSM field(s) for the ACU/BSU control word(s) for the ACU/BSU(s).
4
The BITE status from the LGA diplexer/LNA is continuously sent to the SDU,
with no functional test command necessary or possible. Test results from the
HGA(s), HGA diplexer/LNA, and HPR are reported by the ACU/BSU(s).
The SDU allows up to 30 ± 1 seconds for other system LRUs, except the
5
HSU, which is allowed 60 ± 1 seconds to report their POST results following
initiation of a system-wide functional test. If an LRU fails to report its
functional test results within this time period, but otherwise meets the ARINC
429 bus communication rate requirements, the SDU considers that LRU to
have failed. If no ARINC 429 bus communication is received on a particular
bus, the SDU considers that bus to be inactive.
(b) Test Initiation
1
The correct operation of much of the internal circuitry of the SDU depends
on clocks derived from the high-stability frequency reference generated by
the oven-controlled crystal oscillator (OCXO). Therefore, it is inappropriate to
perform BITE tests until this clock frequency has achieved gross stability. If
the SDU is powered on after having stabilized at a cold external temperature
(e.g., --55° C), it can take several tens of seconds for the frequency drift rate
to be low enough before the phase locked oscillators (PLO) that derive the
dependent clocks can lock onto the OCXO frequency reference.
Honeywell International Inc. Do not copy without express permission of Honeywell.
23- -20- -35
Page 6--5
15 Jul 2006
Advertisement
