Ad9520 Pll Loop Filter; Changes To Ad9520 Pll Loop Filter Section - Analog Devices AD9520-0 User Manual

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AD9520 PLL LOOP FILTER
The AD9520 PLL requires an external loop filter whose
components are tailored for different applications. The third-
order passive configuration shown in Figure 27 usually offers
the best performance for many applications and is the one
found on the evaluation board.
AD9520
LF
VCO
CP
CHARGE
PUMP
BYPASS
Figure 27. PLL Loop Filter
The default loop filter on the
optimized for reference clock cleanup. It has a flat transfer
function with peaking <0.1 dB and loop bandwidths from
0.5 kHz to 10 kHz. In most of these applications, the phase
detector is run at 1 MHz or less.
In the example in the Quick Start Guide to the AD9520 PLL
section, the default loop filter shown in Table 2 results in a PLL
with a loop bandwidth of 2.2 kHz, 80° of phase margin, and
0.05 dB of peaking. The charge pump current for this example
is 1.2 mA.
For clock generation applications in which the reference clock is
relatively low jitter, the high loop bandwidth (BW) loop filter
shown in Table 2 is a better choice. Typical phase detector
frequencies for these applications are 10 MHz to 100 MHz,
and typical loop bandwidths for this loop filter are 50 kHz to
500 kHz, depending on the configuration.
R2
R1
C1 C2 C3
C = 220nF
BP
AD9520 evaluation board is
These recommendations are not a substitute for using
ADIsimCLK™ to determine the best loop filter for a given appli-
cation. ADIsimCLK
and exploration of the capabilities and features of the AD9520,
including the design of the PLL loop filter. The Analog Devices
website has a sample
default loop filter titled:
AD9520EvalBoardExample_148p5MHz.clk.
ADIsimCLK Version 1.3 includes specific support for the
AD9520. However, the AD9516, AD9520, and
the same loop dynamics. Therefore,
can also be used for modeling the
the corresponding version of the AD9516.
at www.analog.com/clocks.
Table 2 shows the correspondence between the components
shown in Figure 27 and those on the evaluation board, as well
as the default values.
Table 2. AD9520
Evaluation
ADIsimCLK Board Location
C1 C25
R1 R5
C2 C22
R2 R2
C3 C31
Rev. A | Page 14 of 16
Evaluation Board User Guide
is a free program that can help with the design
ADIsimCLK file that includes the
ADIsimCLK
AD9520 loop filter by selecting
ADIsimCLK
Evaluation Board Default Loop Filter Values
Clock Cleanup
(Default)
1500 pF
2.1 kΩ
4.7 μF
3 kΩ
2200 pF
AD9520
AD9522 share
Version 1.2
is available
High
Loop BW
62 pF
820 Ω
240 nF
390 Ω
33 pF