Schematic Diagram - Analog Devices ADP5061 Quick Start Manual

UG-467

SCHEMATIC DIAGRAM

J1
CON2
USB- m iniB
J4
8
GND8
7
GND7
6
GND6
5
GND5
adp1720
U3A
pca9557dbg4
3
A0
4
A1
5
A2
R10
1
SCL
SCL
0R
15
RESE T*
8
GND
R13
1k5
SYM 1 OF 1
R14
1k5
JP1
3
3
2
2
1
1
HEA DER_3
ISO_S_F
C7 C8 C9
47u 47u 47u
C7, C8, C9, C10 not assemble
Pads are on the bottom side
J2
CON4
R1 R2
VDD_L DO TP5 VIN_F
56k 100k
U1
J3
1
ADJ
1
2 2
VIN
3
3
VO UT
C1 C2
4
CON3
EN
1u 1u
ISO_S_F
VDDI O
R8
1k5 SYS_EN
J5
6
J6
P0
7
P1
9
P2
10
P3 11 J7
P4
12
P5
13
P6 J8
14
R11
P7
2
SDA
SDA J9
0R
16
VCC
ILED
C6
100nF
R15
TP11 TP12
TP10
1k5
SCL
SDA
SN 5
DIG_IO1 DIG_IO1_S DIG_IO2
Test connectors. Not Assembled
ATEST 1
ATEST 2
C10 C11
47u 22u
ATEST 3
ATEST 4
d
.
Figure 8. ADP5061
VIN_F VIN_S
TP1 TP2
SN 6
C3
10uF
VDDI O
SCL
SDA
R5 R6 R7
N.A. N.A. N.A.
TP6
SYS_EN
TP3 TP4
CBP_S
SN1 0
CBP
TP13 TP14 TP15 TP17 TP19
TP16 TP18
SN 3
SN 9 SN 8
DIG_IO3_S
DIG_IO2_S DIG_IO3 ISO_S_S ISO_S_F ISO_B_S
.
JP2
DIG_IO1 1 2 VIN_F
DIG_IO1_S
3 4
DIG_IO2 5 6 VIN_S
DIG_IO2_S
7 8
DIG_IO3 9 10
DIG_IO3_S
11 12
ILED 13 14
ILE D_S
15 16
17 18
AG ND
19 20
HeaderLarge10 x2
WLCSP Demo Board Schematic
Rev. 0 | Page 10 of 12
Evaluation Board User Guide
ADP5061 WLCSP U2
E3 E2
VIN1 ISO_S1 ISO_S_F
C4
D3 D2
VIN2 ISO_S2
22uF
C3 C2
VIN3 ISO_S3
A4 E1
ISO_B_F
SCL ISO_B1
C5
A3 D1
SDA ISO_B2 22uF
E4 C1
DIG_IO1 ISO_B3
C4 D4
BA T_S NS
DIG_IO2 BA T_S NS
B4 B2
DIG_IO3 THR
A2 A1
SYS_EN ILED
B3
CBP
TP9
SN1 1
R9
10k
R12
J10
10k
C12
10nF
TP20
D1
LED
R16
SN 4
ISO_S_F
0R R17
470R
J11
1
2
3
CON3
ISO_B_F BA T_S NS ILE D_S ILED
VDDI O
JP3
AG ND 1 2
3 4
5 6
BA T_S NS
R18 7 8
ISO_B_F 9 10 SYS_EN
150m
SDA
11 12
ISO_B_S 13 14 SCL
ISO_S_S
15 16
17 18
ISO_S_F
19 20
HeaderLarge10 x2
TP7 TP8
THR
DTES T