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8A3xxxx 72QFN Evaluation Kit Manual
1.3
GPIO Switches, LEDs, and Test Points
An 8-bit dip switch sets the logic levels for seven GPIOs (GPIO0-5 and GPIO9). The GPIO levels for each setting
and the corresponding LED state are listed in the following table (see picture and labels in
Dip Switch Position
Left
Center
High or Low according to the GPIO output setting
Right
When the GPIOs are configured as outputs (such as User-Controlled or LOL indicator), the dip switch for the
corresponding GPIO should be placed in the center position. The LED will indicate the state of the GPIO.
1.4
USB Jack
The board has a USB mini-connector. The other end of the USB cable is a USB Type A connector going to a PC.
1.5
I2C between FTDI, CM Device, and On-board EEPROM
One of the major differences between the 72QFN and 144BGA144 chips is that there is only one serial bus on the
72QFN chip. The I2C bus between the FTDI chip and CM chip is the same bus between the CM chip and the on-
board EEPROM. The on-board EEPROM is used to store device firmware and/or customer's configuration data.
JP12 and JP13 must be jumped between pin 1 and 2 to enable the I2C connections.
Jumper Position
2
EEPROM I
C Path
R31UH0015EU0101 Rev.1.01
Apr 26, 2022
Table 1. GPIO Settings
GPIO Logic Level
Low
High if GPIO is configured as Input
High
Figure 4. GPIO Setting and Status Display Area
Table 2. EEPROM I2C Connections
JP12/JP13
Pin 1 and 2
FDTI and CM Chip;
CM Chip and EEPROM
Figure
LED
On
High if GPIO is configured as Input
High or Low according to the GPIO output setting
Off
JP12/JP13
Pin 2 and 3
4).
N/A
Page 5
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