Bipolar Transistors (13, 3); Jfets (13, 4) - HP 48gII Advanced User's Reference Manual

Bipolar Transistors (13, 3)

These equations for an NPN silicon bipolar transistor are based on large-signal models developed by J.J. Ebers
and J.L. Moll. The offset-voltage calculation differs depending on whether the transistor is saturated or not. The
equations also include the special conditions when the emitter-base or collector-base junction is open, which are
convenient for measuring transistor parameters.
Equations:
q VBE
------------------- -
⎛
k T
⎜
IE = – IES e –
⎝
q VBC
--------------------
⎛
k T
IC = – ICS ⎜ e –
⎝
IS
IS = R IES
ICO = ICS 1 –
k T
VCEsat = ---------- - LN
q
Example:
Given: IES=1E–5_nA, ICS=2E–5_nA, T=26.85_ C, F=.98, R=.49, IC=1_mA, VBC= –10_V.
Solution: VBE=0.6553_V, IS=0.0000098_nA, ICO=0.000010396_nA, ICEO=0.0005198_nA,
IE= -1.0204_mA, IB=0.0204_mA, VCEsat=0_V.

JFETs (13, 4)

These equations for a silicon N-channel junction field-effect transistor (JFET) are based on the single-sided
step-junction approximation, which assumes the gates are heavily doped compared to the channel doping,. The
drain-current calculation differs depending on whether the gate-junction depletion-layer thickness is less than or
greater than the channel thickness. The equations assume the channel is uniformly doped and end effects (such
as contact, drain, and source resistances) are negligible. (See "SIDENS" in Chapter 3.)
q VBE
------------------- -
⎞ ⎛ ⎞
k T
⎟ ⎜ ⎟
1 + R ICS e – 1
⎠ ⎝ ⎠
q V BE
------------------- -
⎞ ⎛ ⎞
k T
1 ⎟ + F IES ⎜ e – 1 ⎟
⎠ ⎝ ⎠
= R ICS IB IE IC +
ICO
--------------- -
ICEO =
F R
1 – F
IC
⎛ ⎞
1 + ----- - 1 – R
⎜ ⎟
IB
⎜ ----------------------------------------------------------- - ⎟
⎜ IC 1 – F ⎟
⎛ ⎛ ⎞ ⎞
----- - --------------- -
R 1 –
⎝ ⎠
⎝ ⎝ ⎠ ⎠
IB F
+ = 0
Equation Reference 5-53