User Manuals: GOWIN GW1NRF-4B Bluetooth FPGA

Manuals and User Guides for GOWIN GW1NRF-4B Bluetooth FPGA. We have 2 GOWIN GW1NRF-4B Bluetooth FPGA manuals available for free PDF download: Programming And Configuration Manual

GOWIN GW1NRF-4B Programming And Configuration Manual (108 pages)

Brand: GOWIN | Category: Semiconductors | Size: 2 MB

Table of Contents
4
List of Figures
6
About this Guide
10
Purpose
10
Related Documents
10
Terminology and Abbreviations
10
Table 1-1 Abbreviations and Terminology
10
Support and Feedback
11
Glossary
12
Table 2-1 Glossary
12
Configuration Modes
14
Littlebee ® Family of FPGA Products
14
Table 3-1 Configuration Modes
15
Table 3-2 Configuration Modes
15
Arora Family of FPGA Products
16
Configuration Process
17
Power-Up Sequence
19
Figure 4-1 por Power-Up Timing
19
Table 4-1 Power Rails Monitored by por Circuits of Different Devices
19
Initialization
20
Configuration
20
Wake-Up
20
User Mode
21
Configuration Pin
22
Configuration Pin List and Reuse Options
22
Configuration Pin List
22
Table 5-1 Configuration Pin List
22
Configuration Pin Reuse
23
Table 5-2 Pin Reuse Options
24
Configuration Pin Function and Application
25
Figure 5-1 Configuring Pin Reuse
25
Table 5-3 Pin Function
25
Figure 5-2 MCLK Frequency Setting
28
Configuration Mode Introduction
30
Configuration Notes
30
Figure 6-1 Recommended Pin Connection
32
Figure 6-2 Power Recycle Timing
33
Figure 6-3 Trigger Timing
33
Table 6-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger
33
JTAG Configuration
34
JTAG Configuration Mode Pins
34
Table 6-2 Timing Parameters for Power-On Again and RECONFIG_N Triggering (Arora Family)
34
Table 6-3 Pin Description in JTAG Configuration Mode
34
Connection Diagram for the JTAG Configuration Mode
35
Figure 6-4 Connection Diagram for JTAG Configuration Mode
35
JTAG Configuration Timing
36
Figure 6-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode
36
Figure 6-6 JTAG Configuration Timing
36
Table 6-4 JTAG Configuration Timing Parameters
36
JTAG Configuration Process
37
Figure 6-7 TAP State Machine
37
Figure 6-8 Instruction Register Access Timing
38
Figure 6-9 Data Register Access Timing
38
Table 6-5 Gowin FPGA IDCODE
38
Table 6-6 Change of TDI and TMS Value in the Process of Sending Instructions
39
Figure 6-10 Read Machine Flow Chart in ID Code State
40
Figure 6-11 the Access Timing of Read ID Code Instruction- 0X11
40
Figure 6-12 Read ID Code Data Register Access Timing
40
Figure 6-13 SRAM Configuration Flow
42
Table 6-7 Count of Address and Length of One Address
43
Figure 6-14 Process of Reading SRAM
44
Figure 6-15 Process of Normal Programming
46
Figure 6-16 Process of Background Programming
47
Table 6-8 TCK Frequency Requirements for JTAG
47
Figure 6-17 the Embedded Flash Erasing Process of T Technology
49
Figure 6-18 the Embedded Flash Erasing Process of H Technology
51
Table 6-9 Readback-Pattern / Autoboot-Pattern
52
Figure 6-19 Process of Programming Internal Flash View
53
Figure 6-20 X-Page Programming
54
Figure 6-21 Y-Page Programming
55
Figure 6-22 Process of Reading Internal Flash
56
Figure 6-23 Process of Reading a Y-Page
57
Figure 6-24 GW1N-4 Background Programming Flow
58
Figure 6-25 Transfer JTAG Instruction Sample & Extest Flow Chart
59
Figure 6-26 Connection Diagram of JTAG Programming External Flash
60
Figure 6-27 Process View of Programming SPI Flash SPI
60
Figure 6-28 Timing Diagram of Sending 0X06 Via GW2A Series JTAG Simulating SPI
61
Figure 6-29 Timing Diagram of Sending 0X06 Via GW1N Series JTAG Simulating SPI
61
Table 6-10 Pin State
61
Figure 6-30 Process of Use Boundary Scan Mode to Program SPI Flash
62
Table 6-11 Status Register Definition
63
AUTO BOOT Configuration (Supported by Littlebee Family Only)
64
Figure 6-31 Connection Diagram of Daisy-Chain
64
Sspi
66
SSPI Mode Pins
66
Table 6-12 SSPI Mode Pins
66
SSPI Configuration Timing
67
Configuration Instruction
67
Figure 6-32 SSPI Configuration Timing
67
Table 6-13 SSPI Configuration Timing Parameters
67
Figure 6-33 Read ID Code Timing
68
Table 6-14 Configuration Instruction
68
Figure 6-34 Write Enable (0X15) Timing
69
Figure 6-35 Write Disable(0X3A00) Timing
69
Figure 6-36 Write Data (0X3B) Timing
70
Connection Diagram for SSPI Configuration Mode
71
Figure 6-37 SSPI Configuration Mode Connection Diagram
71
Figure 6-38 Connection Diagram of Programming External Flash Via SSPI
71
Multiple FPGA Connection View in SSPI Mode
72
Figure 6-39 the Flow of Programming External Flash Via SSPI
72
Figure 6-40 Multiple FPGA Connection Diagram 1
72
Figure 6-41 Multiple FPGA Connection Diagram 2
72
Mspi
73
MSPI Mode Pins
74
Table 6-15 Pin Description in MSPI Configuration Mode
74
Connection Diagram for MSPI Configuration Mode
75
Figure 6-42 Connection Diagram for MSPI Configuration Mode
75
Figure 6-43 Connection Diagram of JTAG Programming External Flash
75
MSPI Mode Configuration Attempts
76
Multi Boot
76
Figure 6-44 Example of Bitstream Image Distribution in Flash Memory
77
Figure 6-45 Input the Start Address for the Next Bitstream
78
Figure 6-46 Set the Programming Address for the External Flash
79
MSPI Configuration Timing
80
Figure 6-47 Connection Diagram for Configuring Multiple Fpgas Via Single Flash
80
Figure 6-48 MSPI Download Timing
80
DUAL BOOT Configuration (Supported by Littlebee Family Only)
81
Figure 6-49 Multiple FPGA Connection Diagram in MSPI Configuration Mode
81
Table 6-16 MSPI Configuration Timing Parameters
81
Figure 6-50 Dual Boot Flow Chart
82
CPU Mode
83
Table 6-17 CPU Mode Pins
83
Configuration Timing
84
SERIAL Mode
84
Figure 6-51 Connection Diagram for CPU Mode
84
Figure 6-52 CPU Mode Configuration Timing
84
Figure 6-53 Connection Diagram for SERIAL Mode
85
Figure 6-54 SERIAL Configuration Timing
85
Table 6-18 Pin Definition in SERIAL Configuration Mode
85
I 2 C Mode
86
Table 6-19 SERIAL Configuration Timing Parameters
86
Table 6-20 Pin Definition in SERIAL Configuration Mode
86
Figure 6-55 Connection Diagram for I 2 C Mode
87
Figure 6-56 I 2 C Mode Timing
87
Table 6-21 I 2 C Configuration Timing Parameters
87
Process of GW1N-2 Configuring or Programming Sram/Flash
89
Figure 6-57 Process of GW1N-2 Configuring or Programming Sram/Flash
89
Bitstream File Configuration
90
Configuration Options
90
Configuration Data Encryption (Supported by Arora Family Only)
91
Definition
91
Figure 7-1 Configuration Options
91
Enter Encryption KEY
92
Enter the Decrypt Key
92
Figure 7-2 Encryption Key Setting Method
92
Programming Operation
93
Figure 7-3 Setting the Decryption Key
93
Figure 7-4 AES Security Configure
94
Programming Flow
95
Figure 7-5 Prepare
95
Figure 7-6 Read AES Key Flow
96
Figure 7-7 Program AES Key Flow
97
Configuration File Size
98
Figure 7-8 Lock AES Key Flow
98
Figure 7-9 Bitstream Format Generation
99
Table 7-1 Gowin FPGA Products Configuration File Size (Max.)
99
Configuration File Loading Time
100
Table 7-2 Loading Frequency of Config File
101
Table 7-3 Loading Time in MSPI Mode
102
Safety Precautions
103
Boundary Scan
105
Figure 9-1 Boundary Scan Operation Schematic Diagram
106
SPI Flash Selection
107

GOWIN GW1NRF-4B Programming And Configuration Manual (97 pages)

FPGA Products

Brand: GOWIN | Category: Semiconductors | Size: 1 MB

Table of Contents
4
List of Figures
6
About this Guide
10
Purpose
10
Related Documents
10
Terminology and Abbreviations
10
Table 1-1 Abbreviations and Terminology
10
Support and Feedback
11
Glossary
12
Table 2-1 Glossary
12
Configuration Modes
14
Littlebee ® Family of FPGA Products
14
Arora Family of FPGA Products
15
Table 3-1 Configuration Modes
15
Table 3-2 Configuration Modes
16
Configuration Pin
17
Configuration Pin List and Reuse Options
17
Configuration Pin List
17
Table 4-1 Configuration Pin List
17
Configuration Pin Multiplexing
18
Table 4-2 Pin Reuse Options
19
Configuration Pin Function and Application
20
Figure 4-1 Configuring Pin Reuse
20
Table 4-3 Pin Function
20
Figure 4-2 MCLK Frequency Setting
23
Configuration Mode Introduction
25
Configuration Notes
25
Figure 5-1 Recommended Pin Connection
27
Figure 5-2 Power Recycle Timing
27
JTAG Configuration
28
Figure 5-3 Trigger Timing
28
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger
28
Table 5-2 Timing Parameters for Power-On Again and RECONFIG_N Triggering (Arora Family)
28
JTAG Configuration Mode Pins
29
Table 5-3 Pin Description in JTAG Configuration Mode
29
Connection Diagram for the JTAG Configuration Mode
30
Figure 5-4 Connection Diagram for JTAG Configuration Mode
30
JTAG Configuration Timing
31
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode
31
Figure 5-6 JTAG Configuration Timing
31
Table 5-4 JTAG Configuration Timing Parameters
31
JTAG Configuration Process
32
Figure 5-7 TAP State Machine
32
Figure 5-8 Instruction Register Access Timing
33
Figure 5-9 Data Register Access Timing
33
Table 5-5 Gowin FPGA IDCODE
34
Table 5-6 Change of TDI and TMS Value in the Process of Sending Instructions
34
Figure 5-10 Read Machine Flow Chart in ID Code State
35
Figure 5-11 the Access Timing of Read ID Code Instruction- 0X11
35
Figure 5-12 Read ID Code Data Register Access Timing
36
Figure 5-13 SRAM Configuration Flow
37
Table 5-7 Count of Address and Length of One Address
38
Figure 5-14 Process of Reading SRAM
39
Table 5-8 TCK Frequency Requirements for JTAG
40
Figure 5-15 the Embedded Flash Erasing Process of T Technology
41
Figure 5-16 the Embedded Flash Erasing Process of S Technology
43
Table 5-9 Readback-Pattern / Autoboot-Pattern
44
Figure 5-17 Process of Programming Internal Flash View
45
Figure 5-18 X-Page Programming
46
Figure 5-19 Y-Page Programming
47
Figure 5-20 Process of Reading Internal Flash
48
Figure 5-21 Process of Reading a Y-Page
49
Figure 5-22 GW1N-4 Background Programming Flow
50
Figure 5-23 Transfer JTAG Instruction Sample & Extest Flow Chart
51
Figure 5-24 Connection Diagram of JTAG Programming External Flash
52
Figure 5-25 Process View of Programming SPI Flash SPI
52
Figure 5-26 Timing Diagram of Sending 0X06 Via GW2A Series JTAG Simulating SPI
53
Figure 5-27 Timing Diagram of Sending 0X06 Via GW1N Series JTAG Simulating SPI
53
Table 5-10 Pin State
53
Figure 5-28 Process of Use Boundary Scan Mode to Program SPI Flash
54
Table 5-11 Status Register Definition
55
AUTO BOOT Configuration (Supported by Littlebee Family Only)
56
Figure 5-29 Connection Diagram of Daisy-Chain
56
Sspi
58
SSPI Mode Pins
58
Table 5-12 SSPI Mode Pins
58
SSPI Configuration Timing
59
Configuration Instruction
59
Figure 5-30 SSPI Configuration Timing
59
Table 5-13 SSPI Configuration Timing Parameters
59
Figure 5-31 Read ID Code Timing
60
Table 5-14 Configuration Instruction
60
Figure 5-32 Write Enable (0X15) Timing
61
Figure 5-33 Write Disable(0X3A00) Timing
61
Figure 5-34 Write Data (0X3B) Timing
62
Connection Diagram for SSPI Configuration Mode
63
Figure 5-35 SSPI Configuration Mode Connection Diagram
63
Figure 5-36 Connection Diagram of Programming External Flash Via SSPI
63
Figure 5-37 the Flow of Programming External Flash Via SSPI
64
Multiple FPGA Connection View in SSPI Mode
65
Mspi
65
Figure 5-38 Multiple FPGA Connection Diagram 1
65
Figure 5-39 Multiple FPGA Connection Diagram 2
65
Table 5-15 Pin Description in JTAG Configuration Mode
66
Figure 5-40 Connection Diagram for MSPI Configuration Mode
67
Figure 5-41 Connection Diagram of JTAG Programming External Flash
67
Figure 5-42 Input the Start Address for the Next Bitstream
68
Figure 5-43 Set the Programming Address for the External Flash
69
Figure 5-44 Connection Diagram for Configuring Multiple Fpgas Via Single Flash
70
Figure 5-45 MSPI Download Timing
70
DUAL BOOT Configuration (Supported by Littlebee Family Only)
71
Figure 5-46 Multiple FPGA Connection Diagram in MSPI Configuration Mode
71
Table 5-16 MSPI Configuration Timing Parameters
71
Figure 5-47 Dual Boot Flow Chart
72
CPU Mode
73
Table 5-17 CPU Mode Pins
73
Configuration Timing
74
SERIAL Mode
74
Figure 5-48 Connection Diagram for CPU Mode
74
Figure5-49 CPU Mode Configuration Timing
74
Figure 5-50 Connection Diagram for SERIAL Mode
75
Figure 5-51 SERIAL Configuration Timing
75
Table 5-18 Pin Definition in SERIAL Configuration Mode
75
I 2 C Mode
76
Table 5-19 SERIAL Configuration Timing Parameters
76
Table 5-20 Pin Definition in SERIAL Configuration Mode
76
Figure 5-52 Connection Diagram for I 2 C Mode
77
Figure 5-53 I 2 C Mode Timing
77
Table 5-21 I 2 C Configuration Timing Parameters
77
Bitstream File Configuration
79
Configuration Options
79
Configuration Data Encryption (Supported by Arora Family Only)
80
Definition
80
Figure 6-1 Configuration Options
80
Enter Encryption KEY
81
Enter the Decrypt Key
81
Figure 6-2 Encryption Key Setting Method
81
Programming Operation
82
Figure 6-3 Setting the Decryption Key
82
Figure 6-4 AES Security Configure
83
Programming Flow
84
Figure 6-5 Prepare
84
Figure6-6 Read AES Key Flow
85
Figure 6-7 Program AES Key Flow
86
Configuration File Size
87
Figure 6-8 Lock AES Key Flow
87
Configuration File Loading Time
88
Figure 6-9 Bitstream Format Generation
88
Table 6-1 Gowin FPGA Products Configuration File Size (Max.)
88
Table 6-2 Loading Frequency of Config File
89
Table 6-3 Loading Time in MSPI Mode
91
Table 6-4 Loading Time in Autoboot Mode
91
Safety Precautions
92
Boundary Scan
94
Figure 8-1 Boundary Scan Operation Schematic Diagram
95
SPI Flash Selection
96

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User Manuals: GOWIN GW1NRF-4B Bluetooth FPGA

GOWIN GW1NRF-4B Programming And Configuration Manual (108 pages)

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GOWIN GW1NRF-4B Programming And Configuration Manual (97 pages)

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