Accelerated Graphics Port (Agp) Bus Interface; Agp 4X Bus - HP Vectra VL800 Technical Reference Manual

Hp vectra vl800: reference manual
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3 System Board
Memory Controller Hub (82850)
MCH Interface
The MCH interface provides bus control signals and address paths via the
Hub Link 8-bit access to the ICH2 for transfers between the processor on
the system bus, Dual Rambus bus and AGP 4x bus.
The MCH supports 32-bit host addresses, allowing the processor to address
a space of 4GB. It also provides an 8-deep In-Order Queue supporting up to
eight outstanding transaction requests on the system bus.
Host-initiated input/output signals are positively decoded to AGP or MCH
configuration space and subtractively decoded to Hub Link 8-bit interface.
Host-initiated memory cycles are positively decoded to AGP or RDRAM, and
are again subtractively decoded to Hub Link 8-bit interface.
AGP semantic memory accesses initiated from AGP to RDRAM do not
require a snoop cycle (not snooped) on the System bus, since the coherency
of data for that particular memory range will be maintained by the software.
However, memory accesses initiated from AGP using PCI Semantics and
accesses from Hub Link interface to RDRAM do require a snoop cycle on the
System bus.
Memory access whose addresses are within the AGP aperture are translated
using the AGP address translation table, regardless of the originating
interface.
Write accesses from Hub Link interface to the AGP are supported.
The MCH supports one Pentium 4 processor at an FSB frequency of 100MHz
using AGTL+ signalling. Refer to
page 71
for a description of the System bus.

Accelerated Graphics Port (AGP) Bus Interface

A controller for the 1.5V AGP (Accelerated Graphics Port) slot is integrated
in the MCH. The AGP Bus interface is compatible with the Accelerated
Graphics Port Specification, Rev 2.0, operating at 133 MHz, and supporting
up to 1 GB/sec data transfer rates. The MCH supports only a synchronous
AGP interface, coupling to the System bus frequency.

AGP 4x Bus

The AGP bus is a dedicated bus for the graphics subsystem, which meets the
needs of high quality 3D graphics applications. It has a direct link to the
MCH.
54

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