HP Vectra VL800 Technical Reference Manual page 57

Read/Write Buffers
System Clocking
RIMM Memory Slots
The PC has four RIMM memory sockets, RIMM A1, RIMM A2, RIMM B1,
RIMM B2, for installing two or four RDRAM memory modules.
Each pair of memory sockets must contain identical memory modules
(identical in size, speed and type). That is, sockets A1 and B1 must contain
identical modules, and sockets A2 and B2 must contain either identical
modules or continuity modules.
If only two RDRAM modules are installed, use the sockets marked A1 and
B1. The other two sockets (A2 and B2) must contain continuity modules.
The MCH defines a data buffering scheme to support the required level of
concurrent operations and provide adequate sustained bandwidth between
the RDRAM subsystem and all other system interfaces (CPU, AGP and PCI).
The MCH operates the System interface at 100 MHz, PCI at 33 MHz and AGP
at 66/133 MHz. Coupling between all interfaces and internal logic is done in
a synchronous manner. The clocking scheme uses an external clock
synthesizer (which produces reference clocks for the host, AGP and PCI
interfaces).
3 System Board
Memory Controller Hub (82850)
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